In my project, I have an action that produces several output files simultaneously. One of them contains rules like the compile target.
Here is a small example makefile of what I would like to run.
SHELL = cmd.exe
rules_InputFiles = makefile
rules_OutputFiles = exec\rules.mk exec\other.mk
$(rules_OutputFiles): exec\rules.temp
.INTERMEDIATE: exec\rules.temp
exec\rules.temp: $(rules_InputFiles)
$(info == generating rules.mk and rules2.mk (due to $?) ==)
if not exist exec mkdir exec
@echo compile: >exec\rules.mk
# precede the second @echo with a tab character
@echo <tab>@echo !!!! compiling !!! >>exec\rules.mk
@echo compile2: >exec\other.mk
# precede the second @echo with a tab character
@echo <tab>@echo !!!! compiling2 !!! >>exec\other.mk
-include exec\rules.mk
Invoking make compile
for this makefile results in the make error message:
*** No rule to make target 'compile'. Stop.
The second invocation runs normal with the output !!!! compiling !!!
I would like run make only once, since this should run on a build server without interaction.
This makefile is a combination of the rules in constructed included makefiles and the generation of multiple targets with an intermediate target.
My question is: can this makefile be modified to achieve my goals?
I tried several workarounds. One of them is to omit the intermediate target and use rules.mk as a marker file. This corresponds to the article of mad-scientists, but doesn't include the necessary dependencies.
Restating the rule as $(rules_OutputFiles): $(rules_InputFiles)
, leads to the recipe executing twice, which is not desired.