Verilog: set expression width inside concatenation operator

Question

So, the problem is that I needed to initialize an array of 32 bit words with a byte pattern inside a loop with a really badly dimensioned looping variable (not my code). Because it was a quick hack, I didn't want to restructure the loop, just to try the test code. So, the working solution was to do the following:

reg [15:0] index;
reg [31:0] data_word;
for (index = 0 ; index < buflen ; index = index+1) begin
  data_dword = (((index*4+'h13)&8'hFF) << 24) | (((index*4+'h14)&8'hFF) << 16) | (((index*4+'h15)&8'hFF) << 8) | (((index*4+'h16)&8'hFF) << 0);
  //I expect to get something like 32'h13141516, 32'h1718191a
end

I thought that I could maybe use a concatenation operator:

data_dword = {((index*4+'h13)&8'hFF), ((index*4+'h14)&8'hFF), ((index*4+'h15)&8'hFF), ((index*4+'h16)&8'hFF)};

But this doesn't work properly. I get 32'h00000016, 32'h0000001a, etc. i.e. only last byte available, all others are overwritten. Why so? I suppose that the length of each sub-expression:

((index*4+'h13)&8'hFF)

is not properly adjusted (is 32 bit for some reason), so the overall concatenation becomes truncated.

What are the results and how do they differ from your expectations? — RaZ

Matthew Taylor Matthew Taylor · Accepted Answer · 2017-12-11T10:16:47

This expression

(index*4+'h14)&8'hFF

is an example of a self-determined expression. The name self-determined names one of two methods Verilog uses to decide how many bits to use to calculate the expression. (The other is context-determined.) The reason why this expression is self-determined is nothing to do with the expression itself and everything to do with the fact that it is one member of a concatenation.

With a self-determined expression, Verilog uses the widest of the operands. In this expression, the widest operands are

'h14

and

which are 32 bits wide. So, Verilog uses 32 bits to calculate the expression and the result is 32 bits wide.

To make your example work, you need something like

(index[7:0]*8'd4+8'h14)

You don't need the &8'hFF, because the result is already 8 bits wide.

A disadvantage of Verilog's liberal ethos is that you do have to be familiar with how it works under the bonnet (the hood), because otherwise it will bite you. You would do well to Google self-determined and context-determined expressions.

Verilog: set expression width inside concatenation operator

1 Answers