Verilog HDL syntax error

Question

everyone, just a quick question on how to fix the following Verilog code, I keep getting errors. Any suggestions?

module bcd_to_seven_seg( B, S);

input wire [3:0]B;
output wire [6:0]S;

reg [6:0] rS;
assign S = rS;

always @(B)
begin
  case({B})
  4'b0000: rS= 7b'1000000;
  4'b0001: rS= 7b'1111001;
  4'b0010: rS= 7b'0100100;
  4'b0011: rS= 7b'0110000;
  4'b0100: rS= 7b'0011001;
  4'b0101: rS= 7b'0010010;
  4'b0110: rS= 7b'0000010;
  4'b0111: rS= 7b'1111000;
  4'b1000: rS= 7b'0000000;
  4'b1001: rS= 7b'0010000;
  endcase

end

endmodule

and here are the errors

Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(32) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(33) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(34) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(35) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(36) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(37) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(38) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(39) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(40) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(41) near text "b";  expecting ";"  
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 10 errors, 0 warnings  
  Error: Peak virtual memory: 556 megabytes  
  Error: Processing ended: Sun Nov 12 11:24:28 2017  
  Error: Elapsed time: 00:00:01  
  Error: Total CPU time (on all processors): 00:00:01

Answer 1

7'b0010001

7' means seven digits

b means you're using binary

0010001 is your number

We've all done the same mistake

Answer 2

I have re-written your code and added comments in places where your code had issues. Please be careful in modelling combinational logic because your code is written in such a way that a latch may get inferred since the case statement doesn't had a default statement. I have written the default case to be x, you may edit it to suit your need.

module bcd_to_seven_seg( B, S);

input wire [3:0]B;
output wire [6:0]S;

reg [6:0] rS;
assign S = rS;

always @(*)                 //Model combinational blocks as always@(*)to avoid latch
begin                       
case(B)                      //Concantenation operator {} not needed
  4'b0000: rS= 7'b1000000;   //Use 7'b instead of 7b'
  4'b0001: rS= 7'b1111001;
  4'b0010: rS= 7'b0100100;
  4'b0011: rS= 7'b0110000;
  4'b0100: rS= 7'b0011001;
  4'b0101: rS= 7'b0010010;
  4'b0110: rS= 7'b0000010;
  4'b0111: rS= 7'b1111000;
  4'b1000: rS= 7'b0000000;
  4'b1001: rS= 7'b0010000;
  default: rs= 7'dx;          //Use default statement else a latch may get inferred
endcase

end

endmodule

Answer 3

It should be 7'b not 7b.

rS = 7'b1000000;

Answer 4

Syntax error < ' > is placed after number of bits ie: 7 in above case not after "b" (which indicates number in binary)

Eg : 7'b0000000; 7'b1100100;