Error (10170): Verilog HDL syntax error at jmd_alub_v.v(31) near text “else”;

1
votes

Error (10170): Verilog HDL syntax error at jmd_alub_v.v(31) near text "else";

expecting this error many times could someone help me out I don't see where the issue is 

module jmd_alub_v(A, B, FS, F, Cout);

    input [3:0] FS;
    input [3:0] A, B;
    output reg [3:0] F;
    output wire Cout;
    wire [4:0] Sum, Incr, Diff, Decr, Shr ;


    assign Sum = {1'b0, A} + {1'b0 ,B} + FS[0];
    assign Diff ={1'b0, A} + {1'b0,~B} + FS[0];
    assign Incr = {1'b0,A} + FS[0];
    assign Decr = {1'b0,A} + 5'b01111;
    assign Shr[4] = A[0];
    assign Shr[3] = A[3];
    assign Shr[2] = A[3];
    assign Shr[1] = A[2];
    assign Shr[0] = A[1];

    always @(A,B,FS)    

    begin

        if (FS == 4'b0000)
        F = A;
        else if (FS == 4'b0001)
        F = Incr[3:0];
        Cout = Incr[4];

        else if (FS == 4'b0010)
        F = Sum[3:0];
        Cout = Sum[4];

        else if (FS == 4'b0011)
        F = Sum[3:0];
        Cout = Sum[4];

        else if (FS == 4'b0100)
        F = Diff[3:0];
        Cout = Diff[4];

        else if (FS == 4'b0101)
        F = Diff[3:0];
        Cout = Diff[4];

        else if (FS == 4'b0110)
        F = Decr[3:0];
        Cout = Decr[4];

        else if (FS == 4'b0111)
        F = A;

        else if (FS == 4'b1000)
        F = ~A;

        else if (FS == 4'b1001)
        F = ~A;

        else if (FS == 4'b1010)
        F = A & B;

        else if (FS == 4'b1011)
        F = A & B;

        else if (FS == 4'b1100)
        F = A | B;

        else if (FS == 4'b1101)
        F = A | B;

        else if (FS == 4'b1110)
        F = Shr[3:0];
        Cout = Shr[4];

        else if (FS == 4'b1111)
        F = Shr[3:0];
        Cout = Shr[4];

        else 

        F = 4'b0000; //default
        Cout = 1'b0; // default
    end
endmodule
2
veriloghdl
FYI: Cout is an inferred latch because it is not defined in every condition. @* is recommenced for combination logic. @(A,B,FS) is legal, however auto sensitivity list are more scalable. You got a long else-if chain, consider using a case-statement instead. – Greg

2 Answers

1
votes

If you are going to put multiple statements in an if or else you need to bracket them with begin and end, for example:

if (FS == 4'b0000)
  F = A;
else if (FS == 4'b0001)
  begin
     F = Incr[3:0];
     Cout = Incr[4];
  end
1
votes

If you use multiple statements in an if/else you need to bracket them with begin and end. While learning Verilog I would recommend using them liberally, as it avoids common errors and makes refactoring easier.

For example:

if (FS == 4'b0000) begin
  F = A;
end
else if (FS == 4'b0001) begin
   F = Incr[3:0];
   Cout = Incr[4];
end

Cout also needs to be declared as a reg. output reg Cout;

A working example is shown EDA Playground. If you are still getting the same error you must have missed at least one of them.

As Greg mentioned in the comments auto-sensitivity lists are preferred as this minimises the chance of a RTL to gate level mismatch. For an automatic sensitivity list always @*

When an output is not fully defined this causes a latch to be inferred, as if not assigned a value it must hold its value which combinatorial logic alone can not do. Latches are not inherently bad but great care must be taken with timing, accidental implication often means the timing has not been considered.

It has also been noted in the comments that it would be better practise to use case statement something like:

always @* begin
  case(FS)
    4'd0 : F = A;
    4'd1 : begin
      F    = Incr[3:0];
      Cout = Incr[4];
    end
    4'd2 : begin
      F    = Sum[3:0];
      Cout = Sum[4];
    end

   endcase
 end

The following two lines could also be rolled into 1 line:

F    = Incr[3:0];
Cout = Incr[4];

Could be come {Cout, F} = Incr[4:0];.