Makefile : Pass a target's dependency as an argument

2
votes

I would like to know if it's possible to pass a makefile target's dependency as an argument. And if it's possible, how to do it.

For example, imagine I have an application which builds from several dependencies

target_full : dep1.o dep2.o dep3.o
    commands

dep1.o : file1 file2
    commands

dep2.o : file3 file4
    commands

dep3.o : file5 file6
    commands

I would like to be able to pass an already compiled dependency as argument.

So if I run make all it will generate dep1.o dep2.o dep3.o from files but if I run make all dep1-file=myDep.o it will generate only dep2.o and dep3.o and use the given dependency WITHOUT recompiling dep1.o from file1 and file2.

In fact I don't want the the first dependency target to be called at all

I imagined something like

ifndef(dep1-file)
    dep1=dep1.o
else
    dep1=${dep1-file}
endif

target_full : ${dep1} dep2.o dep3.o
    commands

${dep1} : file1 file2
    commands

dep2.o : file3 file4
    commands

dep3.o : file5 file6
    commands

However make keep compiling dep1.o from file1 and file2. Maybe it's because of modification dates but I also would like this to NOT be taken in count as I don't care if file1 and file2 are more recent than my custom dependency or not.

EDIT : I should have precised that I have a working solution but it's really ugly though so I'm not fully satisfied with it, I think a better way to do it exist.

However I paste it here so it may facilitate the uderstanding of my issue.

ifndef dep1-file
    dep1=dep1.o
else
    dep1=${dep1-file}
endif

target_full : ${dep1} dep2.o dep3.o
    commands

ifndef dep1-file
${dep1} : file1 file2
    commands
endif

dep2.o : file3 file4
    commands

dep3.o : file5 file6
    commands

I would be glad to have some help to resolve this problem. Thanks in advance

3
clinuxmakefilegnu-make
If you don't want the first the first dependency compiled, then maybe it shouldn't be a dependency. - Christian Gibbons
In my application the dependency is a fpga file which I need to build the application and the OS, however on some computers, the fpga tools are not availables so we need to be able to build either from a precompiled file or from VHDL code. - Arkaik
How is this file having an older modification date than it's dependencies though? Are you copying the file and it's dependencies? - Chris Turner
To test, I copied the generated fpga.bin outside the project folder and cleaned the project, I then reference the file with relative path (../fpga.bin) - Arkaik

3 Answers

4
votes

You can use the command-line-overrides-file feature of variables:

var-dep = dep1.o
target-full : $(var-dep) dep2.o dep3.o

and simply override it on the commandline:

make var-dep=myother.o
1
votes

I think what your looking for is to dynamically create the dependencies as so:

ifndef dep1-file
target_full: dep1.o
else
target_full: $dep-file
endif

target_full: dep2.o dep3.o
     commands ... $^ ...

This means that dep1.o is a dependency of target_full iff dep1-file is not defined. dep1.o is only built if it is a dependency of the top level target.

--------- EDIT ---------------

Another way to do this is to use a variable to represent all the dependencies as so:

DEPS=dep2.o dep3.o
ifndef dep1-file
    DEPS+=dep1.o
else
    DEPS+=$dep1-file
fi

target_full: ${DEPS}
    commands ... $^ ...
0
votes

I do not understand. If you say make dep2.o dep3.o make will build dep2.o and dep3.o. You could even say :

.default:  all
all : target_full

target_full : dep1.o dep2.o dep3.o
    commands

dep1.o : file1 file2
    commands

dep2.o : file3 file4
    commands

dep3.o : file5 file6
    commands

dep1-file : dep2.o dep3.o

If you now say make dep1-file only dep2.o and dep3.o are build the others untouched