How to disable nesting in NVIC Interrupts in ARM Cortex M0+?

3
votes

I have started using ARM Cortex M0+ for GPIO Interrupts. I want to disable nesting feature from ARM Interrupts. Is there any way to do it.? I know by default, nesting is enabled in ARM, I want to disable it.

1
armembeddedinterrupt-handlingcortex-m
Please read this thread on ARM community website. May be this is what you need! – Gaurav Pathak
@anandamu16: Can you elaborate on why you need this feature? You can of course always disable interrupt nesting simply by not using multiple priority levels. The M0+ lacks Cortex M3-style configurable sub-priorities however if you require priority arbitration up to but not including interrupt entry. It is difficult to help you without knowing the particular requirements. To be honest sub-priority masking is somewhat esoteric and should not normally be required unless shaving off the last very cycles of latency, in which case I suggest reconsidering using full preemption. – doynax
@Doynax: Actually I was recently working on Gpio Level Triggered Interrupts. But it was giving me multiple interrupts as soon as push button was pressed (This was because multiple interrupts occur within the time button press completed). I want to have interrupt only once till Gpio Handler exection gets completed. Also I don't want to disable GPIO Interrupt. Moreover, am I right that by default nesting is Enabled in ARM Cortex M0+ Interrupts? – anandamu16
Thanks Gaurav for the reference, I will check the link – anandamu16
@anandamu16: I am still not following you I'm afraid. A single interrupt handler never preempts itself on the Cortex M0+ without some significant contortions. Multiple different interrupt handlers, say on two GPIO ports, may preempt each other if the preempting interrupt source has been set to a higher priority. By default are all configured for the same priority level however and so this should not happen unless you've opted in. – doynax

1 Answers

4
votes

ARM Cortex-M0/M0+ do not support interrupt priority grouping into preemption priority(nestable) and sub-priority (non-nestable) available on the M3/M4/M7 for example.

If you wish to prevent interrupt nesting; it would be necessary to either;

  • set all interrupts to the same priority, or
  • disable and re-enable interrupts on entry and exit to all handlers.

The first of these options is the simplest, but gives no control over execution order (which seldom matters for asynchronous events, but may lead to non-deterministic behaviour and timing). The second does not actually prevent nesting, but does allow nesting only before the lower-priority interrupt has disabled the interrupts - before it has started processing the actual event. The result is behaviour similar to that of sub-priorities available on Cortex-M3 etc.