Generate associative arrays SystemVerilog

1
votes

How can I generate many associative arrays in SystemVerilog with the generate statement?

e.x.

Here is one associative array declaration

logic [8-1:0] memory [*];

How do I generate 10 of them without writing them manual?

1
system-verilog

1 Answers

1
votes

You do not use a generate statement. You can have arrays of arrays

logic [8-1:0] memory [10][int];

P.S. I strongly recommend that use never use [*] as an index type and instead use [int] or some other existing data type. [*] is there for backward compatibility with an older language and using it prevents you from accessing the full power of SystemVerilog.