Different ways to to trigger a SMI for a processor

Question

I am writing some firmware code running in the System Managemnt Mode (SMM) on an Intel platform. I want to fully understand how my SMI handler get started.

I read from the Intel Manual that:

The only way to enter SMM is by signaling an SMI through the SMI# pin on the processor or through an SMI message received through the APIC bus.

And I also read that a synchronous SMI can be triggered by writing to an I/O port.

My understanding is like this:

SMM is just a special operating mode of a processor. Based on my previous experience, whenever I want to change the state of a processor, such as enabling paging or enterring protected mode, I usually modify the control register or Model Specific Registers (MSR). These registers are part of the processor and I can buy it that some internal magic happens if I change some bits of them.

But what does the above I/O port mean? Where does this port pointing to? If writing to a port can trigger a SMI as well, how is the port-writing-approach related to the canonical ways of SMI# pin and the SMI message? And is this port number changeable?

The CPU enters the SMM upon an assertion of the SMI# pin. This assertion can be virtual, by the mean of reprogramming the LAPIC pins configuration and then triggering a suitable interrupt, or physical. Since a pin is, by definition, an input from the external, the CPU needs an external device to drive the SMI# pin physically. This is usually the PCH. The PCH is controlled through MMIO or dedicated IO, the latter takes the form of a write into the IO address space at a specific address. — Margaret Bloom
While memory addresses identify memory locations (a.k.a. words), io addresses identify IO ports. That's just a name, in the end, they are all transactions into the DMI/QPI/DDR bus with their data, address and type (memory vs io). I'm not aware of any standard IO port that asserts the SMI#, I have an Intel Chipset 200 datasheet that has a PM unit that can easily trigger an SMI but that's just a specific case. Each chipset has its layout of registers, ports usually come in continuous blocks, the base address can be changed but the layout cannot. — Margaret Bloom
The layout can be standardised though. Regarding the SMI message: PCI/PCIe introduced MSI (Message Signaling Interrupt) - they are transactions (they are true writes to specific addresses) on the bus that the IOAPIC or LAPIC snoop and convert to an interrupt. Using transactions instead of wires offer huge benefits in term of routeing. One of this MSI can be used to trigger an SMI, thereby the name SMI message. — Margaret Bloom
Are you asking about a standard way to trigger the SMI through IO or how writing to a port can trigger an SMI? The former does not exist, the latter can be elaborated into an answer :) — Margaret Bloom
A thing: what Intel calls an SMI message in the APIC bus is probably an internal message used in the obsolete APIC architecture that used a 3-wire dedicated bus. — Margaret Bloom