clock cycle time of a "slt" instruction on single cycle processor

1
votes

I'm given timing information for

  1. IF (fetch instruction)
  2. ID (decode instruction)
  3. EX (Execute)
  4. MEM (Memory)
  5. WB (write back)

I derived that the clock cycle time of a single cycle processor is just all 5 aforementioned timings summed up, since there is no pipe lining (I hope that's the right justification).

However, if I were to calculate the CC time of a specific instruction such as a slt instruction, then do I only add the times of the components that are relevant? For instance, slt doesn't have to access memory, so can I exclude that in my summation?

1
timemipsclockprocessor
If you fed 1 million back to back slt instructions through, does it take 1 million and 5 clocks or 5 million clocks or somewhere in between to execute those 1 million slt instructions? – old_timer
My guess is that it will take 4 million clock cycles, since it doesn't write to MEM. However, is that sufficient reasoning? – user2639830
so when the first instruction is being executed the second is not being decoded and the third not being fetched? – old_timer
Wouldn't that imply that it's pipe lined? If it doesn't specify it's pipe lined, do I assume so? – user2639830
you say single cycle processor in the title then single processor in the question, which is it? if single cycle then it does all those things in one cycle (other than waiting on memory if there is a memory cycle involved). – old_timer

1 Answers

0
votes

Each instruction in the single-cycle processor takes one clock cycle, so the clock cycle per instruction CPI is 1.

The cycle time Tc (clock period) depends on the critical path, logic design and that the component have delays. The delays are around picoseconds(ps 10^-12).

 Tc = t_pcqPC + 2t_mem + t_RFread + t_ALU + t_mux + t_RFsetup

An example here that show how to calculate the Tc for lw.

delay

The cycle time is

Tc = 30 + 2(250) + 150 + 200 + 25 + 20 = 925 ps

The clock period Tc is shorter for an R-type instruction than lw since they do not have memory access and t_mem = 0. [Harris & Harris].