Where can I write concurrent assertion in monitor?

0
votes

I have to write the following concurrent assertion in my monitor:

assert property (vif.cos == 1 |-> vif_out.y == vif.xi/sqrt(2));

I tried to put it in the run_phase, but I got the following error: Concurrent assertions are not allowed in tasks/class methods.

Where should I put it?

2
system-verilogassertionsuvmsystem-verilog-assertions
You could declare a concurrent assertion inside a module, an interface, a program, a clocking block or a package. Please, correct me if there is any other scope that you could declare a concurrent assertion. – nick_g

2 Answers

1
votes

Please refer to the IEEE Std 1800-2012, Section 14.16 (Concurrent assertions).

A concurrent assertion statement may be specified in any of the following:

  • An always procedure or initial procedure as a statement, wherever these procedures may appear
  • A module
  • An interface
  • A program
  • A generate block
  • A checker

Personally, I would just move that piece of code into the interface file.

0
votes

Concurrent assertions are not allowed in tasks/class methods. You have to put them in a module or similar (interface/program/checker).