Verilog: Aligning valid and invalid bytes from a dynamic input

Question

I'm trying to design a system that takes an 8 byte data input and an 8 bit valid input every clock cycle where each bit on the valid input either validates or invalidates a data byte.

input wire [63:0] d_in;
input wire [7:0]  v_in;

The program should process d_in aligning all the valid bytes as follows.

(where B is a valid byte and X is an invalid byte)

Instance 1:

d_in = B1 B2 X X B3 X B4 B5

d_out = B1 B2 B3 B4 B5 X X X

Instance 2:

d_in = X B1 B2 B3 X B4 B5 B6

d_out = B1 B2 B3 B4 B5 B6 X X

I've mainly worked with algorithms before where all bit manipulation was the same every iteration e.g.assign d_out [7:0] = d_in [15:8]; but the fact that the quantity and order of valid bytes can change with every data input means this strategy cannot be used.

My question:

Is there a way to realise this function in using Verilog or VHDL? If so can someone point me towards a high level solution or some relevant reading so I can understand this concept better. I think if I understood at a high level then I'd be able to take a stab a coding it but currently I'm not even sure what I need to be coding.

Thanks Zach

Ouch! If there is truly no set rule/pattern and it could be any number of bytes at any position - then you will end up with some pretty deep logic. Knowing that, you should use the FPGAs pipelining ability to pre-calculate some nested logics, breaking up the depth and also giving some timing relief for the tools. That's assuming you don't want to buffer the input and shift out bytes, but that would equally not be trivial. — fpga_magik
@fpga_magik If you don't mind can you expand on what you mean by buffer the input signal and shift out bytes? I am interested in this solution. Thanks — Zach

Hida Hida · Accepted Answer · 2017-02-20T14:45:49

Since you asked for high level I will give a pseudocode example of something that might work, or at least get you going.

d_out = '0; //Assuming that the X bytes can be set to zero in the output.
bytes = 0;
for i in range(8)
 if v_in[i]
   d_out[bytes*8 +: 8] = d_in[i*8 +: 8] //Note the +: notation which is not pseudo, but verilog.
   bytes++

Now perform this sequential code in an always block and you should be set.

Note: How the synthesized result from this will look is not entierly clear to me, but i suspect it will generate quite a bit of hardware.

Verilog: Aligning valid and invalid bytes from a dynamic input

2 Answers