I get the following exception in a chisel code.
[info] - should correctly write and read data *** FAILED ***
[info] chisel3.core.Binding$BindingException: 'this' (chisel3.core.UInt@d7): Not bound to synthesizable node, currently only Type description
[info] at chisel3.core.Binding$.checkSynthesizable(Binding.scala:184)
[info] at chisel3.core.Data.connect(Data.scala:139)
[info] at chisel3.core.Data.$colon$eq(Data.scala:204)
[info] at Common.OnChipMemory$$anonfun$1.apply(memory.scala:88)
[info] at Common.OnChipMemory$$anonfun$1.apply(memory.scala:60)
[info] at scala.collection.immutable.Range.foreach(Range.scala:166)
[info] at Common.OnChipMemory.<init>(memory.scala:60)
[info] at Common.memoryTester$$anonfun$3$$anonfun$apply$1$$anonfun$apply$mcV$sp$1.apply(memoryTest.scala:32)
[info] at Common.memoryTester$$anonfun$3$$anonfun$apply$1$$anonfun$apply$mcV$sp$1.apply(memoryTest.scala:32)
[info] at chisel3.core.Module$.do_apply(Module.scala:35)
From this stack trace and some trial and error testing I could find that the line,
read_data := chipMem(data_idx) //line 88
is causing the problem. Code that immediately precedes this is posted below.
val lsb_idx = log2Up(4) // index of lsb in address
val chipMem = Mem(Vec(4, UInt(width = 8)), num_lines) // memory
val data_idx = req_addr >> UInt(lsb_idx) //req_addr is a UInt
val read_data = Bits()
After that I've had no luck finding the cause of the problem. I tried changing read_data to a Vec of UInt and using read() to read from memory.