Verilog - Concatenate multiple defines into one define

Question

I'm looking for a way to concatenate multiple define statements into a singledefine statement, so that I can use it in a case statement.

As an example, have memory addresses that are defined in a header file. I have a case statement that decides if the value should be written to LUTRAM or block ram depending on the address.

I have the following defines:

`define PWM_REPEAT_REG                      (6'h10)         // Number of times to repeat a PWM Pulse
`define PWM_WIDTH_REG                       (6'h14)         // Pulse width in timebase counts
`define PWM_PULSE_PERIOD                    (6'h1c)         // PWM pulse period in timebase counts.

Inside my code i've got a case statement that looks like this:

case(sys_mgr_address) 
    `PWM_REPEAT_REG, `PWM_WIDTH_REG, `PWM_PULSE_PERIOD : begin // Values for block RAM
        ram_a_din               <= sys_mgr_write_data;
        ram_a_addr              <= sys_mgr_address;
        ram_a_wr_enable         <= 1'b1;
        sys_mgr_write_ok        <= 1'b1;
        update_available        <= 1'b1; 
    end 
endcase

The actual design has several addresses and this type of case statement is repeated several times. Rather than type out all the defines over and over for each one, I'd like to create another define that looks like this:

`define PWM_MODULE_BLOCK_RAM_ADDRESSES ({`PWM_REPEAT_REG, `PWM_WIDTH_REG, `PWM_PULSE_PERIOD})

    case(sys_mgr_address) 
    PWM_MODULE_BLOCK_RAM_ADDRESSES : begin // Values for block RAM
        ram_a_din               <= sys_mgr_write_data;
        ram_a_addr              <= sys_mgr_address;
        ram_a_wr_enable         <= 1'b1;
        sys_mgr_write_ok        <= 1'b1;
        update_available        <= 1'b1; 
    end 
endcase

^^ The above code does not work since it's concatenating the numbers into a pretty large vector. I've tried some variations, like without the concatenation braces {}, defining it as text, a few different variations of `` (but I'm not sure what exactly that does).

Is there any way to see the expanded macro before compile? Right now it just gives me an error for most of the ones i've tried which doesn't make troubleshooting easy.

Thanks!

dave_59 dave_59 · Accepted Answer · 2017-01-27T22:19:05

You are thinking too hard. All you need to do is put the comma's the macro

`define PWM_MODULE_BLOCK_RAM_ADDRESSES `PWM_REPEAT_REG, `PWM_WIDTH_REG, `PWM_PULSE_PERIOD

Define macro's are just simple expansions of text.

Verilog - Concatenate multiple defines into one define

1 Answers