VHDL simulation what is the correct delta?

Question

I am currently implementing a MUX, and to test this I've created a generator and a monitor to well generate data as input and monitor its output.

The MUX takes Avalon Streaming interface as input and output and therefor also supports back pressure.

My question is. My test bench run on falling edge while my DUT and input data is generate at rising edge. Both my input clock and my input data is generated at Delta cycle 0. However my back pressure ready signal returning from the DUT and which controls the generator is set at Delta 3. Now this gives some sampling problems because the DUT must only load data every time data from the generator (at delta 0) is valid and the DUT ready is valid (The back pressure signal at Delta 3).

Now if I skew my DUT input clock with 1 ps it fixes the problem. But it feels like that is the wrong approach. What is the correct design principle here. ?

Skew the clock 1 ps or at least move it 4 deltas so i make sure all my signals have been set before rising_edge ?

or

Move the data I generate so it aligns with the DUT output ready signal ?

or

Is it just a decision made from test bench to test bench ?

I've also thought that a clock in a test bench should be generated at delta 0 and everything else must come after.

I am simulating in Riviera-pro

Answer 1

You have various choices:

i) Make everything synchronous. In other words, drive the inputs and sample the outputs on the same edge of the clock as the DUT uses. Afterall, the DUT doesn't suffer any race problems, so if you just extend the clocking strategy to the testbench, everything will work fine. At RTL, but not at gate-level. So if you're doing gate-level sims (which you should be), then this strategy is no good for that.

ii) Clock everything in your testbench off the opposite edge of the clock to the edge the DUT uses. Again, fine for RTL, but whether fine for gate-level depends on the delays through your design.

iii) Drive the inputs to the DUT just after the clock edge and sample the DUT outputs just before it. The clock edge being the edge that the DUT uses. Again, this is fine for RTL, at is the most robust for gate-level, too.

iv) Implement realistic timing for each DUT interface. That ought to work for RTL and gate-level and if it doesn't work for gate-level then the fault is with the DUT not the testbench.