How do I know size of a block “section/offset” in cache design?

2
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I am having trouble understanding how to determine tag/index/offset bits because the wording of questions is confusing me. To clarify, a word in the architecture is 64 bits. Here is the first question:

Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 64-bit memory address references, given as word addresses. 0x03, 0xb4, 0x2b, 0x02, 0xbf, 0x58, 0xbe, 0x0e, 0xb5, 0x2c, 0xba, 0xfd

For each of these references, identify the binary word address, the tag, the index, and the offset given a direct-mapped cache with two-word blocks and a total size of eight blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.

The solution indicates that the offset conists of 1 bit because it takes 1 bit to represent 2 different block "words". So I am trying to visualize the block split up into 2 sections (offsets). How do I know that you are supposed to split the blocks into words (why not bytes)? Clearly the sections in the block determine the number of offset bits needed to represent the block sections. But 2 words is 16 bytes, so why isn't the block split into 16 sections to indicate bytes instead of 2 sections to indicate words? If the block were split up into 16 sections (for all the bytes of 2 words), wouldn't 4 offset bits be needed to determine the 16 different byte sections in the block? I am struggling to know how to figure out how big the block section should be. Does the question saying "two-word blocks" perhaps imply I should visualize the blocks as split into words? Is a 2-word block the same as a 16-byte block? (a word is 8 bytes)

The following question mentions byte-addressing and it is confusing me. How does it relate?:

By convention, a cache is named according to the amount of data it contains (i.e., a 4 KiB cache can hold 4 KiB of data); however, caches also require SRAM to store metadata such as tags and valid bits. For this exercise, you will examine how a cache’s configuration affects the total amount of SRAM needed to implement it as well as the performance of the cache. For all parts, assume that the caches are byte addressable, and that addresses and words are 64 bits.

Calculate the total number of bits required to implement a 32 KiB cache with two- word blocks.

Both questions are from Computer Organization and Design by David Patterson and John L Hennessy

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memorycpu-architecturecpu-cache
Smells like homework. – Turbo J
@TurboJ If you had read further you would see that I have the solutions. "The solution indicates.." Did you even read the post? Nowhere did I ask how to do the questions. I am confused how it is known when to base offset bits on a whole word or a byte.. – Jason Fel
"I'm having trouble understanding this ambiguously-written question" should probably be directed at whoever wrote the question. Without at least seeing all of the accompanying course material for context, it's kinda hard to infer what is supposed to be assumed. The fact that it gives word addresses and asks for word addresses does somewhat suggest a word-addressable cache, though... – Notlikethat
@Notlikethat it is from a textbook (Computer Organization and Design by David Patterson and John L Hennessy). I guess what I mainly want to know is does word addressable mean the block sections are split into words (like first question), and byte addressable means block sections are split into bytes? And if the first question were byte addressable (for the sake of understanding), would there be 4 offset bits instead of the current answer of 1 (since there would now be 16 block sections)? – Jason Fel
@artlessnoise well the textbook mentions that LEGv8 (the architecture studied in the book) is a subset of ARMv8. There are also a ton of references to ARM in the book. There isn't much about LEGv8 online. I couldn't even find a tag for it.. – Jason Fel

1 Answers

2
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How do I know that you are supposed to split the blocks into words (why not bytes)?

Because you have word addresses, not byte addresses. i.e. your memory is word-addressable with addresses of this form.

To get byte addresses from your word addresses, you'd append 3 zeros.

Is a 2-word block the same as a 16-byte block?

Yes, the cache line size is 16 bytes.