Cache memory design - address decoding

0
votes

I was given the following problem:

A CPU generates 32 bit addresses for a byte addressable memory. Design an 8 KB cache memory for this CPU (8 KB is the cache size only for the data; it does not include the tag). The block size is 32 bytes. Show the block diagram, and the address decoding for direct mapped cache memory.

I determined that:

  • 8 bits are needed for indexing
  • 5 bits are needed for block offset
  • 19 bits for the tag.

enter image description here

Is my solution correct? How should I do the decoding?

1
cachingmemorycpu

1 Answers

1
votes

The numbers seem correct, however it is always worth pointing out in your solution that you're taking cache associativity under account. Specifically, 32-8-5=19 is only valid when the cache is directly mapped.

The decoding part is nicely illustrated in your drawing – it's simply the act of taking 32 bits of the address as used by the CPU apart into the tag, index, and offset fields.