Using the "%" character twice in Makefile

Question

Suppose that I want my Makefile rule to be as follows:

For each object file ./obj/%.o, there are two files ./src/%_1.cpp and ./src/%_2.cpp that it depends on (e.g. ./obj/main.o depends on both ./src/main_1.cpp and ./src/main_2.cpp). A naive way of writing the makefile in this case is

./obj/%.o: ./src/%_1.cpp ./src/%_2.cpp

But this approach does not work ... Could any one please suggest how I could define the rule in this situation?

Also, another question I have is - suppose that you define the following rules:

./obj/%.o: ./src/%_1.cpp
./obj/%.o: ./src/%_2.cpp

Then is this "equivalent" to

./obj/%.o: ./src/%_1.cpp ./src/%_2.cpp

Thanks in advance.

Answer 1

A naive way of writing the makefile in this case is

./obj/%.o: ./src/%_1.cpp ./src/%_2.cpp

But this approach does not work

Sure it does (I'm assuming you're actually defining a recipe that should be executed, which you're not showing here). What doesn't work about it?

Also, another question I have is - suppose that you define the following rules:

./obj/%.o: ./src/%_1.cpp
./obj/%.o: ./src/%_2.cpp

Then is this "equivalent" to

./obj/%.o: ./src/%_1.cpp ./src/%_2.cpp

No, not at all. Any pattern rule that doesn't have a recipe deletes that pattern rule. And pattern rules never combine like this.

See Canceling Implicit Rules