Verilog, Module Instantiation with inputs from different modules

Question

Module's Hierarchy where uart_receiver.v=ModuleA, RSD.v=ModuleB, uart_transmitter.V=ModuleC

Suppose I want to Instantiate ModuleA with inputs from different modules, B, and the name of inputs are: WR_EN from moduleB and RD_EN, DT from moduleC

module A(
  input wr_EN,
  input rd_EN,
  input DT,
  output out
);

I tried to do the below with no success, in ISE Xilinx with Verilog

B MODULE

module B(...)
  assign wr_EN = 1;
  ...  
  // Now call module A from B:
  module A A_instance(.wr_EN(wr_EN) );

C MODULE

module C(...) 
  ... 
  assign rd_EN = 0;
  assign DT = 1;
  .... 
  // And then call module A from C
  module A A_instance(.rd_EN(rd_EN), .DT(DT) );

If I call module instances with same names the program doesn't make a second instance, despite the fact that I want one. I searched but I haven't found similar example

Greg Greg · Accepted Answer · 2016-11-09T01:36:13

I tried to clean up your question but I'm still not sure you intend to have two instances of A (one in B the other in C) or if your are trying to share one instance of A between B and C.

An instance represents a physical piece of hardware. The same instance cannot be shared between other module instances. You can route nets to connect instances. For example:

module TOP(...);
  ...
  A A_instance( .wr_EN(wr_EN), .rd_EN(rd_EN), .DT(DT), .out(out) );
  B B_instance( .wr_EN(wr_EN), ... );
  C C_instance( .rd_EN(rd_EN), .DT(DT), ... );
endmodule

You can place A inside of B or C and route the input from the other through a parent level.

module B(
  input rd_EN, // output for C connected at top
  input DT,    // output for C connected at top
  ...
);
  ...
  assign wr_EN = 1;
  A A_instance( .wr_EN(wr_EN), .rd_EN(rd_EN), .DT(DT), .out(out) );
endmodule

or

module C(
  input wr_EN, // output for B connected at top
  ...
); 
  ...
  assign rd_EN = 0;
  assign DT = 1;
  A A_instance( .wr_EN(wr_EN), .rd_EN(rd_EN), .DT(DT), .out(out) );
endmodule

If you placed an instance of A in B and C, then you have two independent instances, even if the input are from a common source.

Verilog, Module Instantiation with inputs from different modules

1 Answers