GNU make - reference targets in another makefile

Question

Preface:

Yes, my makefiles are written badly.
No, I/we didn't write them; we inherited this code base from another company.
I want to know if it's possible to fix my problem WITHOUT rewriting them.

Question

Is there a way to reference targets from another makefile and use those as prerequisites?

Say you have:

all: libs binary

binary: # I need to add prereqs here
    blah
    blah2
    blah3

For binary, I need to targets in other makefiles as prereqs.
I cannot just include those makefiles, and therefore those targets, because those makefiles define identical variables but with different values.

Is it possible to do something like:

binary: C:/mk1:foo C:/mk2:bar
    blah
    blah2
    blah3

UPDATE

In case it's not clear, makefilesC:/mk1 and C:/mk2are part of the same makefile project that is being executed via some top level makefile with make --jobs=X so in theory all makefiles could be being made in parallel.

Short answer: no. Long answer: yes, but you may wind up rebuilding targets unnecessarily. Is that acceptable? — Beta
@Beta yes. Primary objective is minimal modification of makefiles so obviously there'll be compromise. Please proceed. — Bob

Beta Beta · Accepted Answer · 2016-08-13T12:10:06

Sometimes Recursive Make [duhn-duhn-duhnnnn!] is the right tool for the job:

binary: foo bar
    blah
    blah2
    blah3

.PHONY: foo bar

foo:
    $(MAKE) -f mk1 $@

bar:
    $(MAKE) -f mk2 $@

The PHONY forces Make to execute those rules and invoke the other makefiles to (perhaps) rebuild foo and bar even if they already exist (because this makefile doesn't know what prerequisites they may have).

GNU make - reference targets in another makefile

2 Answers