How to constrain integer in VHDL 2008

Question

I want to constrain variable in record. This variable is id_dd in test_vector (record)

type test_vector is record 
            id_dd : integer; 
            stimulus : bit_vector; 
            response : bit_vector; 
        end record test_vector; 

type test_time is record 
            stimulus_time : time; 
            response_delay : delay_length; 
        end record test_time; 

type test_application is record 
            test_to_apply : test_vector; 
            application_time : test_time; 
        end record test_application; 

subtype schedule_test is test_application (test_to_apply (  id_dd (0 to 100) ,
                                                            stimulus (0 to 7),
                                                            response(0 to 9)));

Modelsim Error is :

Constraint for record element "test_vector.id_dd" (at depth 1) cannot apply to non-composite type (std.STANDARD.INTEGER)

How can I constrain id_dd using subtype?

Renaud Pacalet Renaud Pacalet · Accepted Answer · 2016-08-10T07:12:16

According the LRM:

record_constraint ::=
  ( record_element_constraint { , record_element_constraint } )

record_element_constraint ::=
  record_element_simple_name element_constraint

element_constraint ::=
  array_constraint
  | record_constraint

As you can see, an element constraint cannot be a range_constraint, only an array_constraint or a record_constraint. I did not find an explanation about this limitation. Could it be an omission that has been scrupulously implemented by EDA vendors? Or is there another good reason? I'd be interested to know.

How to constrain integer in VHDL 2008

1 Answers