Modelsim fatal error when assigning constant value to signal in procedure

Question

There has been years since i have written any VHDL, so the answer may be obvious.

I am making a testbench to a module i have made, and it uses this procedure to write to a register on UUT:

procedure write_data_proc (
 constant data_value : in std_logic_vector;
 signal  write_en : out std_logic;
 signal data_in : out std_logic_vector;
 signal clk : in std_logic
  ) is
begin
  wait until falling_edge(clk);
  write_en <= '1';
  data_in <= data_value;
  wait until falling_edge(clk);
  write_en <= '0';
end procedure;

It is called from this main stimulation process:

stim_process: process
begin
 mask <= "0000000011111111";
 reset <= '1';
 wait for 2 ns;
 reset <= '0';
 wait for 3 ns;
 write_data_proc("0000000011110000",write_en,data_in,clk);
 write_data_proc("0000000011001100",write_en, data_in,clk);
 write_data_proc("0000000010001001",write_en,data_in,clk);
 read_bytes(3,8,data_read, data_read_master, clk);
end process;

Modelsim gives me a "FATAL ERROR" on the following line in the procedure:

 data_in <= data_value;

I have googled my head off, and i find very little to help me on my way. I hope some of you guys can help me understand what is going on here. If more information is needed, i would be happy to provide more code.

Thanks a lot!

In addition to an MCVE the actual complete error message and/or an indication of who's simulator can be helpful. As Brian's answer demonstrates your code snippets appear to be valid, either leaving a tool implementation issue or a problem external to your code snippets (the latter generally more likely). Creating an MCVE to replicate the issue tends to uncover the problem. — user1155120

user_1818839 user_1818839 · Accepted Answer · 2016-07-06T16:45:25

That's not an MCVE.

It's just a couple of code fragments, missing a lot of vitally important stuff.

Like declarations.

This is an MCVE.

library ieee;
use ieee.std_logic_1164.all;

entity const_value is
end const_value;

architecture test of const_value is

signal mask,data_in : std_logic_vector(15 downto 0);
signal reset, clk, write_en : std_logic;

   procedure write_data_proc (
     constant data_value : in std_logic_vector;
     signal  write_en : out std_logic;
     signal data_in : out std_logic_vector;
     signal clk : in std_logic
  ) is
  begin
    wait until falling_edge(clk);
    write_en <= '1';
    data_in <= data_value;
    wait until falling_edge(clk);
    write_en <= '0';
  end procedure;

begin

stim_process: process
begin
  mask <= "0000000011111111";
  reset <= '1';
  wait for 2 ns;
  reset <= '0';
  wait for 3 ns;
  write_data_proc("0000000011110000",write_en,data_in,clk);
  write_data_proc("0000000011001100",write_en, data_in,clk);
  write_data_proc("0000000010001001",write_en,data_in,clk);
 -- read_bytes(3,8,data_read, data_read_master, clk);
end process;

end test;

Now when I test it, it compiles, elaborates and simulates without fatal errors.

ghdl -a const_value.vhd
ghdl -e const_value
ghdl -r const_value

Or indeed, without any output at all. It would be a good idea to make the testbench self-checking, by adding assert statements in the stimulus process (or another process) testing that the outputs acre the expected values.

Given the exact same MCVE above, what do you get in Modelsim?

If you get the same result as I do, then tell us your real problem : and this time, make an MCVE of it.

Modelsim fatal error when assigning constant value to signal in procedure

1 Answers