Implementing Top Module on ISE Xilinx14.7 verilog

Question

I'm trying to make a counter on verilog using ise xilinx 14.7, webpack version.

Actually, I copied a counter from the book "Digital Design using digilent FPGA Boards" by R. Haskell and D. Hanna in order to understand it and make some modifications.

While syntaxis is all good, when I try to Synthetize the top module, it says unexpected token and illegal redeclaration about variables I'm calling from one of the modules, just like this picture shows. I'm new to verilog, please, if you could tell me what I'm doing wrong, I'd be very thankful.

picture

Unn Unn · Accepted Answer · 2016-06-27T03:21:21

Your problem is the instantiation of the clockdiv module on line 16. The proper syntax for instantiating a module is like so:

module_name instance_name(port_connections);

Where module_name is the name of the module you want to instantiate, instance_name is the name given to this particular instance of the module, and port_connections are the connections of the input, output and inouts of the module, in either .name(connection), or ordered list style. So, I think you meant to say:

clockdiv U1( .mclk(mclk),
             .clr(clr),
             .clk190(clk190),
             .clk48(clk48));

Implementing Top Module on ISE Xilinx14.7 verilog

1 Answers