1
votes

I'm working on an appolication that requires 3x SPI (I'm master in all of them) and SDIO interface, using STM32F446.

2 of the SPIs (SPI1 and SPI2) are sensors that need to be read every 1ms. For SPI1 I need to write 1 byte and the response to that will be the value. For SPI2 I need to write 1 byte and then read 6.

The third SPI (SPI3) and the SDIO are for communication/logging and both of them don't need to transmit data with a fixed period.

Looking at the STM32F46x manual , section 9, it doesn't look like I can trigger DMA transfers with peripherals interupts (that's too bad), but can I do the all thing like:

  1. Timer interrupt every 1ms: inside ISR SPI1 and SPI2 DMA transfers are triggered. DMA transfer fills buffer with received sensor data;
  2. Everytime I need to write to SDIO or SPI3 I start a DMA transfer with less priority then the ones at SPI1 and SPI2.

I'm guessing that SPI1 and SPI2 can perform at parallel since I have 2 DMA controllers and that, if they occur at the same time of SPI2 and SDIO, the later will be blocked until the controller is free. Is that right?

1
I have done that already, 3 SPIS with DMA at max speed, but since SPI1 and SPI2 are slow (1ms is very slow for a stm4) I would make a flag in an interrupt set to 1 and check it in the main code loop if the flag is set. If you do with DMA you will not get more speed since you will need to make exactly the same, each ms relaunch the DMA.hamboy75

1 Answers

3
votes

For SPI1 I need to write 1 byte and the response to that will be the value. For SPI2 I need to write 1 byte and then read 6.

Note that with SPI, reads and writes occur simultaneously, you can read a byte by writing a dummy one, you should take this into account when setting the number of words to transmit.

DMA transfer fills buffer with received sensor data;

Some SPI slaves won't work properly unless you set CS high between transfers. If that's the case with your sensors, you should do that in the receiving DMA stream interrupt. If you are thinking of letting DMA fill up a large buffer automatically, that won't work in this case.

I'm guessing that SPI1 and SPI2 can perform at parallel since I have 2 DMA controllers and that, if they occur at the same time of SPI2 and SDIO, the later will be blocked until the controller is free. Is that right?

They will not be blocked, but interleaved as long as the higher priority transfer does not tie up the DMA bandwidth completely. No SPI transfer can do that, since SPI needs at least 16 clock cycles to transfer a single byte (at least 2 cycles/bit).