How does the user to kernel mode switch occur before the Interrupt Gate descriptor is accessed?

Question

I am currently reading "Understanding the Linux Kernel". I am studying the Interrupts and Exceptions chapter.

I found that when setting up IDT we can use five kinds of gate descriptors in Linux terminology

1. Task Gate (DPL: 0)
2. Interrupt gate (DPL: 0)
3. Trap gate (DPL: 0)
4. System Interrupt gate (DPL: 3)
5. System gate (DPL: 3)

Now i realize that the ones with DPL 3 can be accessed from the user mode. But what about the ones with DPL 0 ? Particularly, interrupt gate.

If an I/O APIC interrupt occurs in User mode, it wouldn't be able to access the Interrupt gate.

So my question is, How does the user mode the kernel mode switch occur before the Interrupt gate is accessed?

Answer 1

When an hardware interrupt happens, the privilege level of the currently executing code can be ignored; the CPU can simply switch to the interrupt's privilege level without checking it.

The Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3A: System Programming Guide, Part 1 says in section 6.12.1.1:

Protection of Exception- and Interrupt-Handler Procedures

The privilege-level protection for exception- and interrupt-handler procedures is similar to that used for ordinary procedure calls when called through a call gate (see Section 5.8.4, “Accessing a Code Segment Through a Call Gate”). The processor does not permit transfer of execution to an exception- or interrupt-handler procedure in a less privileged code segment (numerically greater privilege level) than the CPL.

An attempt to violate this rule results in a general-protection exception (#GP). The protection mechanism for exception- and interrupt-handler procedures is different in the following ways:

• Because interrupt and exception vectors have no RPL, the RPL is not checked on implicit calls to exception and interrupt handlers.
• The processor checks the DPL of the interrupt or trap gate only if an exception or interrupt is generated with an INT n, INT 3, or INTO instruction. Here, the CPL must be less than or equal to the DPL of the gate. This restriction prevents application programs or procedures running at privilege level 3 from using a software interrupt to access critical exception handlers, such as the page-fault handler, providing that those handlers are placed in more privileged code segments (numerically lower privilege level). For hardware-generated interrupts and processor-detected exceptions, the processor ignores the DPL of interrupt and trap gates.

Because exceptions and interrupts generally do not occur at predictable times, these privilege rules effectively impose restrictions on the privilege levels at which exception and interrupt- handling procedures can run. Either of the following techniques can be used to avoid privilege-level violations.

• The exception or interrupt handler can be placed in a conforming code segment. This technique can be used for handlers that only need to access data available on the stack (for example, divide error exceptions). If the handler needs data from a data segment, the data segment needs to be accessible from privilege level 3, which would make it unprotected.
• The handler can be placed in a nonconforming code segment with privilege level 0. This handler would always run, regardless of the CPL that the interrupted program or task is running at.