VHDL, FPGA, 7segment LED with push button

Question

Quartus2V13.0SP1 DE1board VHDL

I am a student of university.

Professor said "do not use CLOCK and 'event".

Yesterday I have done reverse onoff on 7segmentLED.

I edited this question many things today.

Below Code1 is right behavior.

And I want to do it on Code2 without "'event".

--Code1
library IEEE;
use ieee.std_logic_1164.all ;
use IEEE.std_logic_unsigned.all;

entity increase is
    port(
        key0 : in std_logic;
        hex3 : out std_logic_vector(6 downto 0));
end increase;

architecture RTL of increase is
    signal hex3c : integer range 0 to 9;
    begin
        process(key0, hex3c)begin
            if(key0' event and key0 = '0') then
                if(hex3c = 9) then 
                    hex3c <= 0;    
                else        
                    hex3c <= hex3c + 1;             
                end if;
            end if;
        end process;        
    process(hex3c)
    begin   
    case hex3c is
        when 0 => hex3 <= "1000000";
        when 1 => hex3 <= "1111001";
        when 2 => hex3 <= "0100100";
        when 3 => hex3 <= "0110000";
        when 4 => hex3 <= "0011001";
        when 5 => hex3 <= "0010010";
        when 6 => hex3 <= "0000010";
        when 7 => hex3 <= "1111000";
        when 8 => hex3 <= "0000000";
        when others => hex3 <= "0010000";
        end case;
    end process;
end RTL;

and

--Code2
library IEEE;
use ieee.std_logic_1164.all ;
use IEEE.std_logic_unsigned.all;

entity increase is
    port(
        key0 : in std_logic;
        hex3 : out std_logic_vector(6 downto 0));
end increase;

architecture RTL of increase is
    signal hex3c : integer range 0 to 9;
    signal prev : std_logic;
    begin
        process(key0, hex3c, prev)begin
            if(key0 = '0' and prev = '0')then
                if(hex3c = 9) then 
                    hex3c <= 0;
                    prev <= '1';
                else        
                    hex3c <= hex3c + 1;
                    prev <= '1';
                end if;
            elsif(key0 = '1' and prev = '1')then
                prev <= '0';
            end if;
        end process;        
    process(hex3c)
    begin   
    case hex3c is
        when 0 => hex3 <= "1000000";
        when 1 => hex3 <= "1111001";
        when 2 => hex3 <= "0100100";
        when 3 => hex3 <= "0110000";
        when 4 => hex3 <= "0011001";
        when 5 => hex3 <= "0010010";
        when 6 => hex3 <= "0000010";
        when 7 => hex3 <= "1111000";
        when 8 => hex3 <= "0000000";
        when others => hex3 <= "0010000";
        end case;
    end process;
end RTL;

Please give me how to solve this problem.

Really we can realize this?

Does use "no clock and 'event" mean no don't use a clock or does he mean use rising_edge() which is better than 'event. — Paebbels
Maybe I cant use rising_edge and falling_edge in this assignment. Maybe its also out of rule in this assignment. — rararoland

A. Kieffer A. Kieffer · Accepted Answer · 2016-05-23T07:49:17

I've got no evaluation board near me for now to test you're code but the only thing that could be a problem to me now is you're sensitivity list. Try putting count in it so that you're display is updated anytime it changes.

Another suggestion I can give to you is to put every possible case - ie. add the elsestatement - in your process when you use combinatoric processes.

Let me now if it changed anything.

VHDL, FPGA, 7segment LED with push button

1 Answers