Force to L1 cache miss

4
votes

I would like to force my program to miss cache L1 every time ( or nearly every time).

So, my IvyBridge has 32 KB L1 cache and it is 8-way. Therefore, every set contains 8 lines and every line has 64 bytes. First 6 bits of address map to set, 7 last bit map to offset in line, and others bits determine a tag.

How to miss cache? Should I use 8 ( every set has 8 lines) different load operation from the same set?

1
x86
This isn't clear. The easiest way to have a cache miss is to just load an address that isn't currently in the cache. – Oliver Charlesworth
By the way, L1 cache lines are 64 bytes. – Oliver Charlesworth
Why are you trying to do it? What are you trying to accomplish? – Nathan Fellman

1 Answers

4
votes

Yeah, you're on the right track. Using addresses that will all go in the same set will let you test L1 cache misses with the fewest different addresses.

However, 8 different addresses is obviously not enough, since they can all fit into one set. Your best bet is to double or quadruple it, to give the LRU eviction algorithm plenty of chances to evict a line before you come back to it.

Beware of TLB misses, though, if you use too many different addresses on too many pages. 2MB hugepages can help here.