RISCV VERILOG HDL code

Question

I get the following error when compiling RISCV VERILOG HDL on Xilinx ISE:

It says "Unsupported System Function Call" in the following code at line 296 in module vscale_pipeline

295: ifndef SYNTHESIS
296: PC_WB <= $random;

Please show some code, then people could help you to improve/fix your script. Add more detail on your problem. stackoverflow.com/help/how-to-ask — olibiaz
This sounds like the verilog you have isn't supported by Xilinx ISE. I would contact the providers of that code. — user2548418
Is SYNTHESIS defined and defined before this line of code? Compiling order matter. — Greg
Thanks a lot Morgan for your reply: I downloaded the code from the website: github.com/ucb-bar/vscale — Salman Jafri
I got the information from: riscv.org/2015/09/risc-v-in-verilog .. Cannot contact their help service though.. I might be missing something.. — Salman Jafri

CliffordVienna CliffordVienna · Accepted Answer · 2016-05-17T07:32:14

Some synthesis tools define the SYNTHESIS macro so that it is easier to skip non-synthesizable code in synthesis using

`ifdef SYNTHESIS
...
`endif

blocks, as is done in this code.

Xilinx XST does not define this macro by default, so you have to configure XST manually to define the macro during synthesis. See this Xilinx AR for details on how to do that.

RISCV VERILOG HDL code

2 Answers