errors in VHDL code using fpga advantage

Question

I need your help in fixing some errors in my vhdl code. I am using fpga advantage 5.2, its too old, but I am using it because of block diagram, instead of writing the codes with myself.I am developing mips processor using vhdl, I have finished all the blocks except two blocks, which are data memory and instruction memory. Both blocks have the same errors:

Data memory errors:

ERROR: C:/Single-cycle processor/Processor/hdl/dmem_untitled.vhd(34): near "is": expecting: BEGIN ERROR: C:/Single-cycle processor/Processor/hdl/dmem_untitled.vhd(51): near "process": expecting: ';'

instruction memory errors:

ERROR: C:/Single-cycle processor/Processor/hdl/imem_untitled.vhd(38): near "is": expecting: BEGIN ERROR: C:/Single-cycle processor/Processor/hdl/imem_untitled.vhd(53): near "process": expecting: ';'

here is the code for the data memory:

-- hds header_start
--
-- VHDL Architecture Processor.dmem.untitled
--
-- Created:
--          by - Ahmed.UNKNOWN (AHMED-PC)
--          at - 01:58:50 04/21/2016
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.std_logic_textio.all;
library STD;
use STD.textio.all;


ENTITY dmem IS
-- Declarations
 port(clk, we: in STD_LOGIC;
a, wd: in STD_LOGIC_VECTOR (15 downto 0);
rd: out STD_LOGIC_VECTOR (15 downto 0));

END dmem ;

-- hds interface_end
ARCHITECTURE untitled OF dmem IS
BEGIN
process is
    type ramtype is array (63 downto 0) of  STD_LOGIC_VECTOR(15 downto 0);
    variable mem: ramtype;
    variable IADR: INTEGER;

    begin

    IADR:= CONV_INTEGER(a(7 downto 2));
    -- read or write memory
    --loop
        if rising_edge(clk) then
            if (we='1') then mem (IADR):= wd;
            end if;
        end if;
        rd <= mem (IADR);
        wait on clk, a;
    --end loop;
end process;

END untitled;

Also the code for the instruction memory :

-- hds header_start
--
-- VHDL Architecture Processor.IMEM.untitled
--
-- Created:
--          by - Ahmed.UNKNOWN (AHMED-PC)
--          at - 02:17:30 04/21/2016
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;

use IEEE.std_logic_textio.all;
library STD;
use STD.textio.all;



ENTITY IMEM IS
-- Declarations

  port(

     rd: out STD_LOGIC_VECTOR(31 downto 0);
    a: in STD_LOGIC_VECTOR(5 downto 0)
    );

END IMEM ;

    -- hds interface_end
    ARCHITECTURE untitled OF IMEM IS
    begin

    ROM_PROCESS: process(a) is
                                        type MEM is array(0 to 63) of STD_LOGIC_VECTOR(31 downto 0);
                                        variable MEMORY: MEM := (others => X"00000000");
                                        variable IADR: INTEGER;

    begin
            memory(0) := X"00611820" ; -- add $3, $3, $1
            memory(1) := X"ac030004" ; -- sw $3, 4($0)
            memory(2) := X"00221024" ; -- and $2,$1,$2
            memory(3) := X"10220001" ; -- beq $1, $2, SAME
            memory(4) := X"8c010004" ; -- lw $1, 4($0)
            memory(5) := X"0022182a" ; -- SAME: slt $3, $1, $2
            IADR:= CONV_INTEGER(a);
          rd <= MEMORY(IADR);

      end process;

    END untitled;

Unknown Unknown · Accepted Answer · 2016-04-21T02:11:39

The is in a process statement is optional from IEEE Std 1076-1993 forward but not allowed in the -1987 original revision of the VHDL standard.

Remove the is in both files following the process sensitivity lists. This tells us you are analyzing the VHDL with a -1987 compliant tool (for synthesis?).

Also note your use clauses are a mess. Package numeric_std should never be used with Synopsys packages std_logic_arith or std_logic_unsigned. You can simply comment out that use clause.

There's an implicit library clause making the library logical name std available, you don't need that. You aren't using textio either.

Your code would analyzes unchanged with a -1993 revision compliant VHDL tool.

errors in VHDL code using fpga advantage

1 Answers