Errors in VHDL code

Question

I tried to run this code according to suggestion on an other post @Brian Drummond Answer

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use ieee.numeric_std.all;
--use ieee.float_pkg.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pwm_sne is
    Generic(
        sys_clk:integer:=50000000;
        pwm_freq:integer:=100000;
        bits_resolution:integer:=8);
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           k : in  STD_LOGIC_VECTOR (7 downto 0);
           y : out  std_logic);
    end pwm_sne;

architecture Behavioral of pwm_sne is
  signal cnt:std_logic_vector(7 downto 0);
  signal flag:std_logic;
  signal reg:std_logic_vector(7 downto 0);
  --variable duty:std_logic:=0;
  --constant period:integer:-(reg/256)*100;

begin
  process(clk,rst)
  begin
    if rst='1' then
      cnt<="00000000";
    elsif(clk'event and clk='1')then
      cnt<=cnt+"00000001";
    elsif cnt="11111111" then
      flag<='0';
      cnt<="00000000";
    end if;
  end process;

  --
  process(clk,flag)
  begin
    if(flag='0') then
    elsif(clk'event and clk='1') then
      reg<=k;
    end if;
  end process;

  process(cnt,reg,flag)
  begin
    if(flag='0')then
    elsif cnt>=reg then
        y<='1';
        --  y<=duty;
    --elsif cnt=reg then
    --  y<='1';
    elsif cnt<reg then
      y<='0';
      --    y<=duty;
    end if;
  end process;

end Behavioral;

This error occurred during RTL Schematic:

Signal cnt cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

Matthew Taylor Matthew Taylor · Accepted Answer · 2016-03-19T12:43:48

I think your first process perhaps should look like this:

process(clk,rst)
begin
  if rst='1' then
    cnt<="00000000";
  elsif(clk'event and clk='1')then
    cnt<=cnt+"00000001";
    if cnt="11111111" then  -- this was "elsif"
      flag<='0';
      cnt<="00000000";      -- is this line necessary? (cnt should wrap round naturally)
      end if;               -- extra "end if;" now required
    end if;
  end process;

With the elsif you were driving cnt on either edge of the clk, which is not synthesisable.

Whilst there are many ways to code a sequential process, it is wise to be consistent by sticking to a template. Here is one such template for sequential logic with an asynchronous reset, which all synthesis tools should understand:

process(clock, async_reset)  -- nothing else should go in the sensitivity list
begin
    -- never put anything here
    if async_reset ='1' then  -- or '0' for an active low reset
        -- set/reset the flip-flops here
        -- ie drive the signals to their initial values
    elsif rising_edge(clock) then  -- or falling_edge(clock) or clk'event and clk='1' or clk'event and clk='0'
        -- put the synchronous stuff here
        -- ie the stuff that happens on the rising or falling edge of the clock
    end if;
     -- never put anything here
end process;

I notice some other things that ought to be fixed, too:

i) The second process does not have an asynchronous reset. Here is the corresponding template for a sequential process without an asynchronous reset:

process(clock)  -- nothing else should go in the sensitivity list
begin
    -- never put anything here
    if rising_edge(clock) then  -- or falling_edge(clock) or clk'event and clk='1' or clk'event and clk='0
        -- put the synchronous stuff here
        -- ie the stuff that happens on the rising or falling edge of the clock
    end if;
     -- never put anything here
end process;

I don't know the design intent, but the second process doesn't fit this template. Here it is, conforming to the template:

process(clk)
begin
  if(clk'event and clk='1') then
    if(flag='0') then
      reg<=k;
    end if;
  end if;
end process;

So, flag should not be in the sensitivity list.

Again, I can only guess your design intent, so I can't say this code meets your requirements.

ii) You never drive flag high.

iii) You don't need parentheses in if statements.

Errors in VHDL code

1 Answers