'No paths to report' in TimeQuest on VHDL code

Question

I'm writting some code in Altera Quartus 13.1 and I can't check my Fmax for my entity in TimeQuest. I get 'No paths to report'. The code is given below:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

library NTRU;
use NTRU.NTRU.all;

entity ModuloAdder is
    port(
        FirstHalf   : in Int32 := 0;
        SecondHalf  : in Int32 := 0;    
        Start           : in std_logic := '0';
        clk             : in std_logic;
        Result      : out Int32 := 0;
        ReadyOut        : out std_logic
        );
end ModuloAdder;

architecture a1 of ModuloAdder is
begin
process(clk, Start, FirstHalf, SecondHalf)
variable sum: integer range 63 downto -63:=0;
begin
    if clk'event and clk ='1' then
        if Start = '1' then 
            sum := (FirstHalf + SecondHalf) mod 32;
            if sum > 32 then
                Result <= sum mod 32;
            elsif sum < -3 then
                Result <= sum+32;
            else 
                Result <= sum;
            end if;
            ReadyOut <= '1';
        else 
            ReadyOut <= '0';
            Result <= 0;
        end if;
    end if;
end process;
end a1;

My question is why this problem occur. When I change variable sum to signal, there is everything ok, but I want this in one clock cycle. This code works fine in ModelSim and is giving fine results.

Were there any clues in the synthesis report? Also, check the process sensitivity list carefully... — user_1818839
I added clk to sensivity list, same result. Sythesis reports shows only informations that 'Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" '. , but in TimeQuest in 'Clock' tab there is my clk. — TheJeronimek
Now "clk" is in the sensitivity list, the others should be unnecessary. I think that Synth message is saying you need to add a timing constraint to "clk". — user_1818839

happydave happydave · Accepted Answer · 2014-10-30T14:08:49

It looks like there are no register to register paths in your design, so TimeQuest can't report an Fmax. To report an Fmax, you'd have to tell it the relationship between the I/O signals and the clk (using set_input_delay and set_output_delay). Or, if you first register your inputs (e.g. by adding FirstHalfReg <= FirstHalf), you should see register to register, paths, and should get an Fmax for those internal paths.

'No paths to report' in TimeQuest on VHDL code

1 Answers