Using Fixed point in VHDL

Question

In my filter design , I am using fixed point arithmetic and using sfixed for signals. The design synthesizes with all timing met but my functional simulation and post synth/P&R simulation do not match after arith logic blocks.. Giving a small ex below, where I see that crf_int_r does not match in Post synth simulation.. Can someone help me understand , whether it is not synthesized properly or some other issue for a mismatch between functional and post synth simulation..Using Xilinx ISE 14.7 and VHDL 200X option in ISE.

signal add_alpha1_r : sfixed(5 downto -13) ;
signal add_alpha2_r : sfixed(6 downto -13) ;
signal crf_r : sfixed(17 downto -13) ;
signal crf_int_r : sfixed(17 downto -7) ; 
signal alpha_log : sfixed(4 downto -13) ;
signal imgdel_r_d4 : sfixed(4 downto -13) ;
signal imgsum_d2 : sfixed(4 downto -13) ; 

  add_alpha1_r <= imgdel_r_d4 - imgsum_d2  ; --19.13   
  add_alpha2_r <= alpha_log + add_alpha1_r  ; -- 20.13  
  crf_r      <= add_alpha2_r * beta ; -- 31.13   
  crf_int_r    <= crf_r(17 downto -7);

Declarations, pre and post synthesis operand and result binary values would be nice. Are you using non-default package generics? — user1155120
I am using ieee fixed point pkg's. use ieee_proposed.fixed_float_types.all; — kaps
In post synth netlist , some signals are generated with declaration as std_logic_vector(5 downto -3). Such signals give error in VCOM. And I am changing such signals to type std_logic_vector1 as per info from xilinx. But still I get a mismatch , though I see multipliers have been inferred.. — kaps
Who's simulator? The reason I ask is the cfr_r assignment get's a bound check failure with -2008 instantiated package ieee.fixed_generic_pkg. Please add new information to your question. You missed beta declaration, I set it to the same as add_alpha2_r. Binary operand and result values? — user1155120
You need to write a proper question. Show the code with all the declarations, provide a set of inputs and the corresponding outputs, and tell us how the output is different from your expected output. If the output is correct in functional sims and incorrect in post-P&R then tell us exactly what the difference is. "converting to integer and comparing to Matlab" and "all -ve" is no use to anybody. — EML

Martin Zabel Martin Zabel · Accepted Answer · 2015-12-19T14:49:55

You encountered a synthesis bug. Making a Minimal, Complete, and Verifiable example from the code presented in the comments, I have tried to synthesize this with ISE 14.7 and VHDL-200X option on:

library ieee;
use ieee.std_logic_1164.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

entity sfixed_test is
  port (alpha_log : out sfixed(4 downto -13));
end sfixed_test;

architecture rtl of sfixed_test is
  constant alpha : sfixed(10 downto 0) := "00001111000"; -- 120
  type rom_t is array(0 to 2047) of sfixed(4 downto -13);
  constant alpha_rom : rom_t := (120 => "111111111111111111",
                                 others => "000000000000000000");
begin  -- rtl
  alpha_log <= alpha_rom(to_integer(alpha));
end rtl;

XST reports the following warning:

Warning: "::fixed_pkg:TO_INTEGER (sfixed): metavalue detected, returning 0"

A quick look into the RTL or Technology Map Viewer shows, that all outputs were connected to ground instead of VCC as intended in my example.

The problem is the implementation of to_integer as described bewlow. You can work around this, if you change the reading from the ROM to:

alpha_log <= alpha_rom(to_integer(unsigned(std_logic_vector(alpha))));

and also include the package ieee.numeric_std. Then everything works fine.

Further notes: The warning message refers to line 5085 ff. of ieee_proposed/fixed_pkg_c.vhd shipped with ISE. It reads:

if (Is_X (arg)) then
  assert NO_WARNING
    report fixed_pkg'instance_name
    & "TO_INTEGER (sfixed): metavalue detected, returning 0"
    severity warning;
  return 0;
end if;

Is_X(arg) checks whether the argument contains a U, X, Z, W, or -. It fails here if arg (which is alpha) is a constant. But, it works when alpha is a signal (input).

Using Fixed point in VHDL

1 Answers