How can I fix the warning " HDLCompiler: 1007 - Element index 7 into memp is out of bounds" when I describe the hardware RAM, using Verilog in Xilinx?

0
votes

I have the following hardware description of a dual port RAM memory :

module MemoryRAM #(parameter  RAM_ADDR_BITS = 4, RAM_WIDTH = 8)
(CLK, RAMEnableLSB, RAMEnableMSB, WriteMemory,LoadData, Address, OutputRAMMEM);


input  RAMEnableLSB, RAMEnableMSB ,WriteMemory;
input CLK;


reg [RAM_WIDTH-1:0] RAM1 [(2**RAM_ADDR_BITS)-1:0];
reg [RAM_WIDTH-1:0] OutputData1 = 0,OutputData0 = 0;


input [RAM_ADDR_BITS-1:0] Address;
input [2*RAM_WIDTH-1:0] LoadData;
output [2*RAM_WIDTH -1:0] OutputRAMMEM;



always @ (posedge CLK)
begin
    if(RAMEnableMSB) begin
        if (WriteMemory) 
        begin
            RAM1[Address+1] <= LoadData[2*RAM_WIDTH-1:1*RAM_WIDTH];    //     Bit MSB
            OutputData1 <= LoadData[2*RAM_WIDTH-1:1*RAM_WIDTH];
        end
        else 
        begin
            OutputData1 <= RAM1[Address+1];           //     Bit MSB
        end
     end
     else
        OutputData1 <= 0;
end


always @ (posedge CLK)
begin
    if(RAMEnableLSB) begin
        if (WriteMemory) 
        begin
            RAM1[Address] <= LoadData[1*RAM_WIDTH-1:0*RAM_WIDTH];  //     Bit LSB
            OutputData0 <= LoadData[1*RAM_WIDTH-1:0*RAM_WIDTH];
        end
        else 
        begin
            OutputData0 <= RAM1[Address];           //     Bit LSB
        end
    end else
        OutputData0 <= 0;
end


assign OutputRAMMEM = {OutputData1,OutputData0};
endmodule

When I synthesized in Xilinx ISE 14.7, a message tells me that the synthesis is correct. If I also executed a behavioral simulation the result is the expected.

However, If I executed a Post-Route simulation a warning message appear:

WARNING:HDLCompiler:1007 - "N:/O.61xd/rtf/verilog/src/unisims/ARAMB36_INTERNAL.v" Line 1050: Element index 7 into memp is out of bounds

And the simulation does not work!!!. A important point is that I am using the ISim simulator. If I described the hardware of a sigle port RAM the same warning also appear.

Could anyone say me how can I solve this warning?

1
verilogxilinxhdlxilinx-ise

1 Answers

0
votes

Not sure about "index 7" but I do notice that address for MSB can go out of range. The max index for RAM1 is 15. Max address for your MSB is (15+1).

You can add an extra index to RAM1 or wrap the address back to 0 if it overflows. If you warp it, then every entry if accessible to MSB and LSB.

Two was to warp the address. With a mod operation:

RAM1[(Address+1)%(2**RAM_ADDR_BITS)] <= LoadData[2*RAM_WIDTH-1:1*RAM_WIDTH];

Or calculate the MSB address and mask out the its MSB bit when indexing RAM1:

wire [RAM_ADDR_BITS:0] AddressMSB = Address+1;
...
RAM1[AddressMSB[RAM_ADDR_BITS-1:0]] <= LoadData[2*RAM_WIDTH-1:1*RAM_WIDTH];  //  Bit MSB
...