SystemVerilog immediate assertion failure at time 0fs

Question

I have added an immediate assertion to test that two registers are not programmed to the same value at any given time. I get a failure at time 0fs because all values are uninitialized and are 'x'.

always @(*) begin
  assert_reg_val_cmp:
  assert (reg != 1'b1) else $error("...error msg...");
end

Is there a way to cleanly disable this assertion only at initial time? I could use reg !== 1'b1 comparison, which compares 'x' too, but I want to catch any 'x' states after 0fs.

Do you have a reset signal that you can check before checking the assertion? — igon
I can, but I am not sure how the syntax will work. I know the syntax for concurrent assertions, but where would disable iff (reset !== 1'b1) go? — Wilderness
disable iff doesn't work an immediate assertion. You can use: assert (reset === 1'b1 || reg != 1'b1) else $error("...error msg..."); or if (reset == 1'b1) assert (reg != 1'b1) else $error("...error msg..."); — Greg
Thank you. I had inverted the polarity on reset and that is why it did not work. Your suggestion worked. — Wilderness

dave_59 dave_59 · Accepted Answer · 2015-12-09T23:37:04

If you are using SystemVerilog,please use always_comb instead of always @(*). The latter has a problem in that it does not execute if one of the inputs turns out to be a constant.

If you want to make sure a register is initialized at time 0, then used a deferred assertion.

always_comb begin
  assert_reg_val_cmp:
  assert #0 (reg != 1'b1) else $error("...error msg...");
end

But why do you not want to use a concurrent assertion for this?

SystemVerilog immediate assertion failure at time 0fs

1 Answers