SystemVerilog assertion

0
votes

I have the following interfaces:

interface tx_in_interface (input bit clk, input bit tx_srstn);
   //dut input
   logic [15:0] xi;   
   logic [15:0] xq;   
   logic [15:0] sin;  
   logic [15:0] cos;  
   int  chind2;   
endinterface



interface tx_out_interface (input bit clk, input bit tx_srstn);
   //dut output
   logic [15:0] y;
   int chind2;   
endinterface

I want to check that every time sin equal to 1(dec) y will be xi/sqrt(2), and every time cos equal to 1(dec) y will be xq/sqrt(2).

Can I do it with a specific kind of systemVerilog assertion (with no use of scoreboard or coverage)?

2
system-verilogassertionssystem-verilog-assertions
Yes. Two SVA assertions would do the trick, one to check that y is xi/sqrt(2) when sin is 1,the other to check that y is xq/sqrt(2) when cos is 1. It is not clear what you are asking. Do you know about SVA assertions? - Matthew Taylor
@Matthew Taylor - I know, but new in this issue (SVA assertions). Can you give code example for one of the case? - sarad
Here's a SystemVerilog Assertions Tutorial on my company's website. - Matthew Taylor
@Matthew Taylor - I have already started to read it. The problem that I have not seen yet asssertion which involve signals from different interfaces. - sarad
You can use hierarchical references just like you would anywhere else in Verilog/SystemVerilog, eg assert property (...module_inst.tx_in_interface.inst.sin == 16'd1 -> ...module_inst.tx_out_interface.inst.y == ...module_inst.tx_in_interface.inst.xi/sqrt(2)) ... - Matthew Taylor

2 Answers

1
votes

Yes I think you can simple write the following 2 properties.

property sin_check;
  (sin == 'd1) |-> y == (xi/sqrt(2));
endproperty

property cos_check;
  (cos == 'd1) |-> y == (xq/sqrt(2));
endproperty
0
votes

Following 2 assertions can verify your specified condition:

//Creating instances of interface 
tx_in_interface tx_i; 
tx_out_interface tx_o;

//Checking conditions 
assert property (@posedge tx_i.clk) (tx_i.sin == 1) |-> tx_o.y == (tx_i.xi/sqrt(2)); 
else $error("Sine output error!");

assert property (@posedge tx_o.clk) (tx_i.cos == 1) |-> tx_o.y == (xq/sqrt(2)); 
else $error("Cos output error!");

SystemVerilog Assertions Tutorial by Duolos is an excellent resource.