How to pass vector to module without changing value?

Question

I want to write an array multiplier and I have two modules ArrayMultiplier,Top.

In the Top module I have three array result, a1, a2.

module Top();
   reg [4*5-1:0] a1;
   reg [5*3-1:0] a2;
   wire [4*3-1:0] result;
   integer i,j;
   initial begin
     for(i=0;i<4;i=i+1) begin
       for(j=0;j<5;j=j+1) begin
         a1[i*5+j]=1'b1;
       end
     end
     for(i=0;i<5;i=i+1) begin
       for(j=0;j<3;j=j+1) begin
         a2[i*3+j]=1'b1;
       end
     end
   end  
   ArrayMultiplier #(4,5,3) test(result,a1,a2);
endmodule

And ArrayMultiplier:

module ArrayMultiplier(result,a1,a2);
  parameter a1R=0;
  parameter a1C=0;//a1C=a2R.
  parameter a2C=0;
  output reg[(a1R*a2C)-1:0] result;
  input [(a1R*a1C)-1:0] a1;
  input [(a1C*a2C)-1:0] a2;
  integer i,j,k;
  initial begin
    //$display("a1R=%d a1C=%d a2C=%d",a1R,a1C,a2C);
    for(i=0;i<4;i=i+1)
      for(j=0;j<5;j=j+1)
        $display("%d a1=%d ",i,a1[i*5+j]);
    for(i=0;i<a1R;i=i+1) begin
      for(j=0;j<a2C;j=j+1) begin
        result[i*a2C+j]=0;
      end
    end
    for(i=0;i<a1R;i=i+1) begin
      for(j=0;j<a2C;j=j+1) begin
        for(k=0;k<a1C;k=k+1) begin
          result[i*a2C+j]=result[i*a2C+j]+(a1[i*a1C+k]*a2[k*a2C+j]);
          $display("res=%d a1=%d a2=%d",result[i*a2C+j],a1[i*a1C+k],a2[k*a2C+j]);
        end
      end
    end
  end
endmodule

I have initialized a1, a2 but when I pass them to ArrayMultiplier module they just have x value.

I don't know what is happening.

Please help.

Thanks.

sharvil111 sharvil111 · Accepted Answer · 2015-12-03T16:15:02

You are not overriding the parameters of ArrayMultiplier module.

By default, the parameters like a1R,a1C and a2C are initialized to 0, if these are not overridden while instantiating module, then the vectors a1 and a2 are created of zero size.

Looking at your Top module, mapping a1R=4, a1C=5 and a2C=3, and instantiating the module, solves the error of displaying x. The module instantiation is as follows:

ArrayMultiplier #(4,5,3) test(result,a1,a2);

This solves your problem. For more information on parameterized modules, have a look at Parameterized Modules and Module Parameters in Verilog links.

How to pass vector to module without changing value?

2 Answers