object notation in verilog

Question

I am newbie to verilog hdl.

For testing a single cycle mips cpu, I am trying to use the following notation to initialize a register from the testbench.

CPU.IM.memory[i] = 32'b0

Here, CPU is one module which has a declaration for IM (another module) and memory is declared as a reg in it.

However, the Quartus verilog compiler is complaining that it cannot find the object reference. Is the above supported? I have a similiar problem in loading instructions in memory, I dont want to be able to do it from the testbench, instead of hardcoding or changing it in IM.

TestBench.v

for(i = 0; i < 32; i = i + 1) begin 
    CPU.IM.IMReg[i] = 32'b0; 
end

CPU.v

IM IM( 
//inputs 
    .address (pc), 
    .clk (clk), 
    .out (Instruction) 
);

IM.v

module IM ( address, clk, out); 
input [31:0] address; 
input clk; 
output reg[31:0] out; 
reg[31:0] IMReg[31:0];

Error being thrown Error (10207): Verilog HDL error at TestBench.v(31): can't resolve reference to object "IMReg"

There is an entry about this error at Quartus help here and this forum question, seems like tool specific issue. — sharvil111

wilcroft wilcroft · Accepted Answer · 2015-11-30T17:33:05

It's hard to tell what you're trying to do without seeing more of your code, but what I'm guessing is that you're trying to assign an internal signal (ie a signal not present on the input or output port list) of a module a value from inside a different module. Unless that value is a constant parameter, you can't do this. Only parameters, localparams, and signals on the port list (inputs, outputs, and inouts) are externally visible.

Usually, memories are initialized off of either a .hex or .mif file, which can be altered to represent the desired initial state.

object notation in verilog

1 Answers