printing "still alive message" only once for multiinstance bindings in system verilog

Question

I have the following problem I like to solve. I use bindings to bind system Verilog assertions to the RTL. To make sure that the binding is enabled I added at the beginning of the binding code a "sva xyz binding is alive" message. This binding will be instantiated many times because the block I bind my assertion to is used many times in the RTL. Now I got as many "is alive" messages as instantiated blocks, which spams the log file of the simulation.

Is there a way to prevent this ? The only way I have in mind is using a toplevel variable and access this variable via a hierarchical access, but this is just an ugly workaround.

This is the message I added at the beginning of my sva binding code

   `ifndef _ALARM_FLAG_SVA_ON
       `define  _ALARM_FLAG_SVA_ON
       initial begin
         $display ("-I-: SVA binding for ALARM_FLAG is alive.");     
       end
    `endif

The problem here is that I read the file only once, which means that the ifndef is correct for all multiple instance bindings.

thanks rth

Answer 1

You can assign a bit in a package. Use the $test$plusargs to control the overall enable disable of the feature.

package my_pkg;
  bit alarm_sva_flag = $test$plusargs("alarm_sva_flag");
endpackage

Then in your initial block from from your binded module, check the bit valuevalue. If set, reset it and display, else skip. This will the display message only once.

if (my_pkg::alarm_sva_flag) begin
  my_pkg::alarm_sva_flag = 0; // <- disable : prevent others from displaying
  $display ("-I-: SVA binding for %s is alive.");
end

When you run simulation with the +alarm_sva_flag runtime argument, then the message will only display once. Without +alarm_sva_flag, no message will be displayed.

---

UVM has another approach. It is a steep learning curb, but a very powerful and versatile once mastered. Looking writing your own uvm_report_catcher identify the message, how often, and when to display. The website Verification Academy and the paper UVM Message Display Commands - Capabilities, Proper Usage and Guidelines by Cliff Cummings are some sources to learn about UVM and UVM messaging.

Answer 2

Simple solution:

Create a package (for example paTestConfig), that you include into your testbench. In this package add

localparam ALARM_FLAG_SVA_ON 0

now do your check for each binding:

if (ALARM_FLAG_SVA_ON)
   begin
     $display ("-I-: SVA binding for %s is alive.", modulename);     
   end

So when you want to debug your bindings you can just change the define in paTestConfig to 1 and your messages will show. You should also extend this package to include everything you can parameterize in your testbench.

Sleek, scalable, solution:

Use the reporting capabilities of the UVM package. The UVM package has special reporting macros where you can set the "importance-level"(verbosity) of each message. You can then silence your lower level infos while still getting info from more important messages.

import uvm_pkg::*;
`include "uvm_macros.svh"

**your binding here**
`uvm_info("Binding", $sformatf("Sva binding for module %s is alive", modulename), UVM_DEBUG);

To make this work you first have to figure out how to run your simulations with UVM, which may be simple or very complicated based on your compiler. When you are running with UVM, add the line below to your command line argument to change verbosity levels.

+UVM_VERBOSITY=UVM_DEBUG //Turn on DEBUG level infos

or

+UVM_VERBOSITY=UVM_FULL //Turn off DEBUG level infos