wire in always block/case statement - Verilog

1
votes

Following is a sample code that uses case statement and always @(*) block. I don't get how the always block is triggered and why it works even when x is declared as wire. 

wire [2:0] x = 0;
always @(*)
begin
case (1'b1)
  x[0]: $display("Bit 0 : %0d",x[0]);
  x[1]: $display("Bit 1 : %0d",x[1]);
  x[2]: $display("Bit 2 : %0d",x[2]);
  default: $display("In default case");
endcase
end

Any help is appreciated.

Thanks.

3
caseverilogsystem-verilog

3 Answers

2
votes

As we know, reg can be driven by a wire, we can definitely use a wire as the right hand side of the assignment in any procedural block.

Here, your code checks which bit of x is 1'b1 (of course giving priority to zeroth bit). Lets say x changes to 3'b010. Then, Bit 1 shall be displayed and so on. Now, if x=3'b011 then Bit 0 is displayed since zeroth bit is checked first.

As you can see, there is no assignment to x, the procedural block only reads its value. Moreover, the system task $display also reads the value of x.

There is no change of signal value from this block. Hence, this code works fine. If, by chance, we had something like x[0] = ~x[0] instead of $display, then this code shall provide compilation issues.

More information can be found at this and this links.

1
votes

Here, this always block does not assign a value to a x, but it just checks a value of x. So it's a legal use of wire.

1
votes

So, the explanation to the part of your question about how always @(*) is triggered is as follows :

"Nets and variables that appear on the right-hand side of assignments, in subroutine calls, in case and conditional expressions, as an index variable on the left-hand side of assignments, or as variables in case item expressions shall all be included in always @(*)."

Ref: IEEE Std 1800-2012 Sec 9.4.2.2

As an extension of @sharvil111's answer, if your code was something like this

always @(*)
begin

case (sel)
x[0]: $display("Bit 0 : %0d",x[0]);
x[1]: $display("Bit 1 : %0d",x[1]);
x[2]: $display("Bit 2 : %0d",x[2]);
default: $display("In default case");

endcase
end

The procedural block would be triggered whenever there is a change in sel signal or x i.e. it would be equivalent to always @(sel or x).