Verilog hdl magnitude comparator error

Question

I have written the simple code below for a magnitude comparator. The 6 bits of C give the values of A=B,A!=B,etc; However, i am getting the following error when i run the code. How can i fix the error?

c2q39.v:7: error: C['sd5] is not a valid l-value in testbench.m.
c2q39.v:3:      : C['sd5] is declared here as wire.

My code is

module mag(A,B,C);
input [3:0] A,B;
output [5:0] C;

always @ (A or B)

assign C[5]=(A==B);
assign C[4]=(A!=B);
assign C[3]=(A>B);
assign C[2]=(A<B);
assign C[1]=(A>=B);
assign C[0]=(A<=B);
endmodule

module testbench;
reg [3:0] A,B;
wire [5:0] C;
mag m(A,B,C);

initial
begin
A=4'b0000;B=4'b0000;
#10 A=4'b1000;
#10 B=4'b1001;
#10 A=4'b1000;
end

initial
$monitor("%0d %b %b %b",$time,A,B,C);

endmodule

You have mixed the procedural block(always) and continuous assignment(assign) statements. The LHS of procedural block statement is always a reg. So, either declare C as reg and add begin..end in always block, along with removal of assign statement; or simply remove always block with rest of the stuff as it is. — sharvil111

ssgr ssgr · Accepted Answer · 2015-11-01T03:05:34

It is not a good idea to use assign statement in always block ( for more details refer here ). So you can define your output C as reg and implement the following way:

module mag(A,B,C);
input [3:0] A,B;
output reg [5:0] C;

always @ (A or B)
begin
 C[5]=(A==B);
 C[4]=(A!=B);
 C[3]=(A>B);
 C[2]=(A<B);
 C[1]=(A>=B);
 C[0]=(A<=B);
end
endmodule

The other way to implement is just use assign statements.

module mag(A,B,C);
input [3:0] A,B;
output [5:0] C;

//always @ (A or B)

assign C[5]=(A==B);
assign C[4]=(A!=B);
assign C[3]=(A>B);
assign C[2]=(A<B);
assign C[1]=(A>=B);
assign C[0]=(A<=B);

endmodule

Verilog hdl magnitude comparator error

1 Answers