0
votes

How can I design my own MAC layer function to access Ethernet chip instead of using altera IP function. My board is DE1-SoC with cyclone V 5CSEMA5F31C6 chip. The pins to access Ethernet chip are made to be HPS pins which I can't assign my own signals to.

2
You can't. From the Cyclone 5 handbook, Introduction to the Hard Processor System - "The HPS and FPGA portions of the device each have their own pins. Pins are not freely shared between the HPS and the FPGA fabric. The HPS I/O pins are configured by software executing in the HPS. Software executing on the HPS accesses control registers in the system manager to assign HPS I/O pins to the available HPS modules." The handbook is found on the CDROM image that came with the DE1-SoC board.user1155120

2 Answers

1
votes

It is possible for Cyclone V as well. I have my own Ethernet IP working on the fpga side in a DE1-SOC board using the HPS pins. I used them through the pin multiplexing feature of the hps component. You have to configure them and make the hps boot the preloader code for that configuration. However, you cannot use the DDR feature (consequently you cannot achieve 1Gbps) in the cyclone v (Altera said that). For the process, you should set the pin multiplexing, generate Qsys and compile Quartus. This process creates the folder spl_bsp. Then you have to create a SD card with the image provided by Altera (the image contains all the partition requiered). After this you are able to make the preloader: 1) bsp-generate-files.exe --settings ./software/spl_bsp/settings.bsp --bsp-dir ./hps_isw_handoff/soc_system_hps_0 2) cd software/spl_bsp/ 3) make 4) make uboot 5) alt-boot-disk-util.exe -p preloader-mkpimage.bin -a write -d e // e is the drive of the SD card 6) cp uboot-socfpga/u-boot.img /cygdrive/e

Finally, put the SD card in the fpga kit and programm the FPGA. The HPS boots from the SD card and the pin multiplexing matrix configures the pins for output.

0
votes

This is possible on the new Arria 10 SoC, but not in Cyclone V. Arria 10 has shared I/Os that are configurable to the HPS or the FPGA.