Accessing wire/reg dimensions in Verilog

Question

In VHDL there are many predefined attributes that can help in making code more generic, e.g.:

signal sig : std_logic_vector(7 downto 0);  
-- ...  
for i in sig'range loop ...

Is there a similar way to access the dimensions of a Verilog wire or reg?

Of course it's possible to define the boundaries of each wire or reg as a parameter as in:

parameter w_upper = 7;  
parameter w_lower = 0;  
wire [w_upper:w_lower] w;

but that seems like a lot of overhead and far less elegant than VHDL.

I have seen that SystemVerilog has things like $bits, $size, $high and $low, but what about Verilog-2005 or earlier?

Qiu Qiu · Accepted Answer · 2015-06-04T16:52:28

Verilog-2005 doesn't have equivalents for VHDL attributes ('size, 'left, 'right, 'high, 'low, etc.).

As you mentioned in your question, that feature was introduced in SystemVerilog, where you have following attributes: $dimensions, $unpacked_dimensions, $left, $right, $low, $high, $increment, $size.

Accessing wire/reg dimensions in Verilog

1 Answers