VHDL: Convert String to Std_Logic_Vector

Question

I'm writing a sha-256 hash function in VHDL and it takes in a String. I need to convert this string to a std_logic_vector of bits. So, I must somehow extract the bits from the characters of the String, but I'm not sure of the best way. As far as I can tell there does not exist a built in function to do this in any of the libraries.

Is my only option to loop through each index of the string and use a case block to map the characters to their respective 8-bit ASCII counterparts? Or is there some way to convert a character to bits?

I'd like to get the conversion in either bin or hex...is that what you mean? — Ryan McClure
...Why the downvote? This is an entirely valid question and hasn't been asked/answered anywhere else. — Ryan McClure
Duplicate of VHDL: Is there a convenient way to assign ascii values to std_logic_vector?. The accepted answer is equivalent to Jonathan's albeit not as succinct, and was instead making the point you could find an answer by actually searching, contrary to your own assertion). Your question shows a lack of research effort. — user1155120

Jonathan Drolet Jonathan Drolet · Accepted Answer · 2015-05-29T02:54:35

You can convert a string to bits with a function like this (untested):

function to_std_logic_vector(a : string) return std_logic_vector is
    variable ret : std_logic_vector(a'length*8-1 downto 0);
begin
    for i in a'range loop
        ret(i*8+7 downto i*8) := std_logic_vector(to_unsigned(character'pos(a(i)), 8));
    end loop;
    return ret;
end function to_std_logic_vector;

I don't think type string is synthesisable, so this function is only useful for simulation or static initialization.

VHDL: Convert String to Std_Logic_Vector

1 Answers