VHDL bidirectional testbench-UUT module

0
votes

I am a bit new to the VHDL world and need some guidance on something that may seem trivial to many.

That I want is to build a bidirectional Testbench-UUT module,where I would be able to control the inputs’ flow given by the testbench, from my main module.

Actually,I need to say to my testbench when I am ready to process the new input.

Something like, raising a flag from my ‘main’ module that would enable the testbench to push a new input in.That could possibly be controlled by an if statement, and if that flag is ‘up’ allow the next input to flow in.

I am fiddling around with inout ports,but haven’t managed sort it out this way...

Could you please assist me, and if possible give some short example code?

G

2
vhdl

2 Answers

1
votes

One fairly straightforward way of doing this is to use wait until in your stimulus process in your testbench. If you have a data ready signal output from the block you're testing, it just look like:

STIMULUS_PROCESS: process
    while (not loopCondition) loop
        -- Apply stimulus to the inputs
        wait until dataReady = '1';
        -- Read the outputs and repeat.
    end loop;
end process;
0
votes

Finally,i had to include a sensitivity list in my testbench process,that would contain any flag would be useful for triggering the next input. G