A piece of VHDL code for injecting error to input data is shown below:
entity error_test
Port (
clk : in STD_LOGIC;
force_error_i : in STD_LOGIC_VECTOR(1 downto 0);
din : in STD_LOGIC_VECTOR(127 downto 0);
dout : out STD_LOGIC_VECTOR(127 downto 0)
);
end error_test;
architecture Behavioral of error_test is
signal single_error_2 : std_logic_vector(127 downto 0) := x"00000000000000000000000000000001";
signal double_error_2 : std_logic_vector(127 downto 0) := x"00000000000000000000000000000003";
signal triple_error_2 : std_logic_vector(127 downto 0) := x"00000000000000000000000000000007";
signal din_errinj_2 : std_logic_vector(127 downto 0);
process (force_error_i, din, single_error, double_error, triple_error)
begin
case (force_error_i) is
when "00" =>
din_errinj_2 <= din;
when "01" =>
din_errinj_2 <= din xor single_error_2(127 downto 0);
when "10" =>
din_errinj_2 <= din xor double_error_2(127 downto 0);
when "11" =>
din_errinj_2 <= din xor triple_error_2(127 downto 0);
when others =>
din_errinj_2 <= din;
end case;
end process;
end Behavioral;
This module works fine in the main design and also in the testbench simulation.
But the issue is with the code coverage tool analysis. The code coverage tool(Reviera-PRO from Aldec) shows that when the input force_error_i(2) is "00" then when "00" is covered and also when others condition is also covered! Is the when others condition redundant here? Or do we need others statement but something else is wrong here?
