cannot be driven by primitives or continuous assignment

3
votes

I got

reg OUT; cannot be driven by primitives or continuous assignment.

error.

The Counter module is:

module Counter(
    input             clk,
    input             clear,
    input             load,
    input             up_down, // UP/~DOWN
    input[3:0]        IN,
    input             count,
    output reg[3:0]   OUT
    );
    always @(posedge clk, negedge clear)
    if (~clear) OUT <= 4'b0000;
    else if(load) OUT <= IN;
    else if(count)
    begin
       if(up_down) OUT <= OUT + 1'b1;
       else OUT <= OUT - 1'b1;
    end
    else OUT <= OUT;
endmodule

And the testbench is:

module test;
   .
   .
   .
   reg [3:0] IN;
   reg [3:0] OUT;

   Counter c1(clk, clear, load, up_down, IN, count, OUT);
endmodule

The error is in the Counter c1(clk, clear, load, up_down, IN, count, OUT); line.

1
verilog

1 Answers

6
votes

The problem is that the test module has this declaration:

reg [3:0] OUT;

A reg should not be connected to a module output.

Change reg to wire in test, then make sure no other signal drives the OUT net in test:

wire [3:0] OUT;