Update data when clock goes low - VHDL

Question

I need to set output data when clock goes low and not to next rising_edge, I've modified a code to work in this way, but I've this warning:

Clock on register Empty tied to a constant Clock on register Full tied to a constant

This is the code:

elsif rising_edge(Clock) then  
                if (Head = Tail) then
                    if Looped then
                        FullVar := '1';
                    else
                        EmptyVar := '1';
                    end if;
                else
                    EmptyVar := '0';
                    FullVar := '0';
                end if;
   else
      Full <= FullVar;
      Empty <= EmptyVar;
   end if;
end process;

To eliminate this warning I've modified code in this way:

elsif rising_edge(Clock) then  
                if (Head = Tail) then
                    if Looped then
                        FullVar := '1';
                    else
                        EmptyVar := '1';
                    end if;
                else
                    EmptyVar := '0';
                    FullVar := '0';
                end if;
   end if;
   Full <= FullVar;
   Empty <= EmptyVar;
end process;

But when I compile code and simulate I've a higher delay before flag is asserted(in the corrected code without warnings). Why is that? Also, code works, but it's correct this type of code or data should be always updated when rising_edge?

As Brian Mentioned, the falling_edge() function does what you need. Be aware that this effectively creates a new mesochronous clock domain delayed by half a period. You will have less setup time available on the crossings between these domains and need to account for that with timing constraints in a real world design. — Kevin Thibedeau
No, this is not what I mean. For example this is a FIFO, it assert empty flag not when FIFO goes empty, but at next clock it has gone empty. It this way empty flag is asserted when clock goes low after it gone empty in rising_edge of same clock cycle. What I ask is, since it doesn't seems to me a standard coding but this code works, can it create errors in long runs? — Yaro
if rising_edge(clock) then can not have a else case. It's not synthezisable. — Paebbels

Rasmus B. Sorensen Rasmus B. Sorensen · Accepted Answer · 2015-05-08T07:53:50

Yes, you should always use rising_edge(Clock), unless you 'really' need a second clock domain. In your case you do not need a second clock domain.

There is also no reason to use variables in you example. The following code will raise Empty after a rising_edge of the clock, if Head is equal to Tail and Looped is '1' before the rising edge.

check : process (Clock)
if rising_edge(Clock) then
    if Head = Tail then
        if Looped then
            Full <= '1';
        else
            Empty <= '1';
        end if;
    else
        Empty <= '0';
        Full <= '0';
    end if;
end if;
end process;

If you want the have Empty raise before the rising edge you should do this combinatorially, like this:

check : process (Head,Tail,Looped)
Empty <= '0';
Full <= '0';
if Head = Tail then
    if Looped then
        Full <= '1';
    else
        Empty <= '1';
    end if;
end process;

I hope this helps.

Update data when clock goes low - VHDL

1 Answers