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Will "Exclusive L2 Cache" in Cortext-A9 improve performance? ARM Cortext-A9 Technical Reference Manual has some explanation about "Exclusive L2 Cache":

8.1.5. Exclusive L2 cache The Cortex-A9 processor can be connected to an L2 cache that supports an exclusive cache mode. This mode must be activated both in the Cortex-A9 processor and in the L2 cache controller.

In this mode, the data cache of the Cortex-A9 processor and the L2 cache are exclusive. At any time, a given address is cached in either L1 data caches or in the L2 cache, but not in both. This has the effect of greatly increasing the usable space and efficiency of an L2 cache connected to the Cortex-A9 processor. When exclusive cache configuration is selected:

  1. Data cache line replacement policy is modified so that the victim line always gets evicted to L2 memory, even if it is clean.
  2. If a line is dirty in the L2 cache controller, a read request to this address from the processor causes writeback to external memory and a linefill to the processor.
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Performance is always 'it depends'. You get more cache memory. However, the flushing/cleaning and invalidate operations become much more complex. You need to refine the question part 'improve performance' to something meaningful. Context switches with some OS patterns may become more complex. Your question is far more intelligent than most; unfortunately, it is hard to answer in the current form.artless noise

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The main advantage of exclusive caches is that you maximize the cache capacity: The total amount of unique data cached in your cache hierarchy is equal to the sum of the sizes of each cache level.

On the other hand, if you have an inclusive cache hierarchy, where the Last level cache is inclusive of the lower levels, then the total amount of unique data cached in your cache hierarchy is equal to the size of the last level cache.

Both schemes have pros and cons and the best setup is very dependent on your workloads.