I use a Cortex A9 CPU with two L1 caches: One for data and the other for the instructions. Cache policy could be either "write-back" or "write-through". The Cortex-A9 Technical Reference Manual part "7.1. About the L1 memory system" said that the data L1 cache has :
- one 32-byte eviction buffer
- a 4-entry, 64-bit merging store buffer
I don't understand the difference between these two buffers. In my opinion :
- "eviction buffer" is used to hold dirty evicted lines before it is written to the RAM
- "merging store buffer" is used to hold data before it is written to the RAM
I guess that "eviction buffer" is only used with write-back policy while "merging store buffer" is only used with write-through policy but i'm not sure of that hypothesis.
Thanks and sorry for my basic English.