Make using implicit rule instead of explicit?

Question

Here is my entire Makefile:

TGT = call
OBJS = main.o

.PHONY : clean

$(TGT) : $(OBJS)
        $(CC) -o $@ $^

%.o : %.s
        $(AS) -o $@ $<

%.s : %.c
        $(CC) -S -o $@ $<

clean :
        $(RM) $(TGT) *.o *.s

When I run make, I was expecting:

main.s gets built from main.c
main.o gets built from main.s
call gets built from main.o

Instead what make is doing is:

$ make
cc    -c -o main.o main.c
cc -o call main.o

Any ideas why it is using the implicit rule for *.o files rather than the explicit one I specified? Note that if I manually create the *.s file first, it uses my explicit rule:

$ make main.s
cc -S -o main.s main.c
$ make
as -o main.o main.s
cc -o call main.o

Am I just fundamentally misunderstanding something with Make? Shouldn't it recognize that main.s is a prerequisite for main.o, and build main.s using the rule I specified?

pmod pmod · Accepted Answer · 2015-03-07T21:16:03

You can disable all built-in suffix rules just by setting empty value for suffix targets:

.SUFFIXES:

And then set own suffixes:

.SUFFIXES: .o .s

Running make with flags -r or --no-builtin-rules should do the same. See here.

Make using implicit rule instead of explicit?

1 Answers