ModelSIM ALTERA error

Question

I have the following code, to test in Altera ModelSim one memory ROM.

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;
USE ieee.numeric_std_unsigned.all;

ENTITY hex_vhdl_vhd_vec_tst IS
END hex_vhdl_vhd_vec_tst;

ARCHITECTURE hex_vhdl_arch OF hex_vhdl_vhd_vec_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL t_sig_address : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL t_sig_clock   : STD_LOGIC;
SIGNAL t_sig_q       : STD_LOGIC_VECTOR(7 DOWNTO 0);

COMPONENT hex_vhdl
  PORT(
    address : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
    clock   : IN STD_LOGIC;
    q       : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
  );
END COMPONENT;

BEGIN
  tb : hex_vhdl
  PORT MAP(
    -- list connections between master ports and signals
    address => t_sig_address,
    clock   => t_sig_clock,
    q       => t_sig_q
  );


TEST: PROCESS
variable L : natural;
begin
  --clock
  for L in 0 to 2048 loop
    t_sig_clock <= '0';
    WAIT FOR 25 ns;
    t_sig_clock <= '1';
    WAIT FOR 25 ns;
    t_sig_address <= std_logic_vector(to_unsigned(L, 11));
  end loop;
  t_sig_clock <= '0';
  wait;
END PROCESS TEST;

END hex_vhdl_arch;

The code in the PROCESS part, was designed by me.

I'm tempted not use more the address change step by step...

Before, I had to make a PROCESS for each bit address.

The only line that does not compile is

t_sig_address <= std_logic_vector(to_unsigned(L, 11));

# ** Error: hex_vhdl.vht(70): (vcom-1136) Unknown identifier "to_unsigned".

So I added the following line at the beginning

USE ieee.numeric_std_unsigned.all;

But, started a following error

# ** Error: (vcom-11) Could not find ieee.numeric_std_unsigned.
# ** Error: hex_vhdl.vht(30): (vcom-1195) Cannot find expanded name "ieee.numeric_std_unsigned".
# ** Error: hex_vhdl.vht(30): Unknown expanded name.

I made these arrangements with the clues, that I found in the links bellow

Illegal type conversion VHDL

Convert Integer to std_logic_vector in VHDL

I do not know why not worked!!!

These libraries work right in quartus II, but so seems not work in ModelSim.

Could someone help me with this? :)

Also: variable L is never used. Lint report: sigasi.com/vhdl-code-check?ID=28031531 — Philippe
Yes, this seems obvious... Because, if not there was a correct declaration of the library in line 3, the sentence in line 42 became wrong... In so, the variable L declared on line 34, will never be used !!! simple. — songa

fru1tbat fru1tbat · Accepted Answer · 2015-01-19T18:54:29

The proper package for to_unsigned() is ieee.numeric_std, which includes thr unsigned type as well as associated operator overloads and conversion functions. numeric_std_unsigned, on the other hand, has only function overloads for when you want to treat std_logic_vector signals implicitly as unsigned, i.e. without explicit typecasting or conversion.

ModelSIM ALTERA error

1 Answers